Special memory (SM) and system symbol names
D.14 SMB36-SMB45 (HSC0), SMB46-SMB55 (HSC1), SMB56-SM65 (HSC2), SMB136-SMB145 (HSC3), SMB146-
S7-200 SMART
System Manual, V2.3, 07/2017, A5E03822230-AF
813
Table D- 12 HSC3 configuration and operation
: Counter status bits are valid only while the CPU is executing an inter-
rupt routine that a high-speed counter event triggered.
SM136.0–
Reserved
HSC3 current counting direction status bit: TRUE: Counting up
HSC3_Status_6 SM136.6 HSC3 current value equals preset value status bit: TRUE: Equal
HSC3_Status_7 SM136.7 HSC3 current value is greater than preset value status bit: TRUE: Greater
SM137.0–
Reserved
HSC3 direction control bit: TRUE: Count up
HSC3 update direction: TRUE: Update direction
HSC3 update preset value: TRUE: Write new preset value to HSC3 preset
HSC3_CV_Update SM137.6 HSC3 update current value: TRUE: Write new current value to HSC3 cur-
HSC3 enable bit: TRUE: enable
You use SMD138 to set HSC3 current value to any value you choose. To
update the current value, write the new current value to SMD138; write 1 to
SM137.6; and execute the HSC instruction. The instruction then writes the
new current value to HSC3's current count register.
You use SMD142 to set HSC3 preset value to any value you choose. To
update the preset value, write the new preset value to SMD142; write 1 to
SM147.5; and execute the HSC instruction. The instruction then writes the
new preset value to HSC3's preset register.
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