Configuration
3.12 Communication with the CPU
Configuration - DNP3
62 Configuration Manual, 11/2018, C79000-G8976-C508-01
Communication with the CPU
Communication with the CPU
Using the first three parameters you specify the CPU access by the TIM in the CPU scan
cycle. You will find the structure of the CPU scan cycle in the section Read cycle (Page 115).
The fourth parameter "Frame memory size" decides the size of the send buffer of the TIM for
frames of data points that are configured as an event.
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Wait time between two scan cycles of the CPU memory area
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Max. number of write jobs
Maximum number of write jobs to the CPU memory area within a CPU scan cycle
●
Maximum number of low-priority read jobs from the CPU memory area within a CPU scan
cycle.
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Here, you set the size of the frame memory for events (send buffer).
The size of the frame memory is divided equally among all configured communications
partners. For information on the size of the frame memory, see "Performance data and
configuration limits".
You will find details of how the send buffer works (storing and sending events) as well as
the options for transferring data in the section Process image, type of transmission, event
classes (Page 113).
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TIM monitoring / CP monitoring
Via the watchdog bit, the CPU can be informed of the status of the telecontrol
communication of the communications module.
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Using this function, the CP can make its time of day available to the CPU.
You will find details in the STEP 7 information system.
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