Functions
2.8 Undervoltage and Overvoltage Protection 27/59 (Optional)
SIPROTEC, 7SD80, Manual
E50417-G1140-C474-A1, Release date 09.2011
120
Overvoltage Zero Sequence System 3V
0
Figure 2-49 depicts the logic diagram of the zero sequence voltage element. The fundamental frequency is nu-
merically filtered from the measuring voltage so that the harmonics or transient voltage peaks remain largely
harmless.
The triple zero sequence voltage 3·V
0
is fed to the two threshold elements 59G-1-3V0PICKUP (address 3722)
and 59G-2-3V0PICKUP (address 3724). Combined with the associated time delays 59G-1-3V0 DELAY (ad-
dress 3723) and 59G-2-3V0 DELAY (address 3725) these elements form a two-element overvoltage protec-
tion for the zero sequence system. Here too, the dropout ratio can be set (59G RESET), address 3729). Fur-
thermore, a restraint delay can be configured which is implemented by repeated measuring (approx. 3 periods).
The overvoltage protection for the zero sequence system can also be blocked via a binary input „>59-3V0
BLOCK“. The elements of the zero sequence voltage protection are automatically blocked as soon as an asym-
metrical voltage failure was detected („Fuse–Failure–Monitor“, also see Section 2.14.1, margin heading „Fuse
Failure Monitor (Non-symmetrical Voltages)“ or when the trip of the mcb for voltage transformers has been sig-
naled via the binary input „>FAIL:Feeder VT“ (internal indication „internal blocking“).
According to Figure 2-49 the device calculates the voltage to be monitored:
3·V
0
= V
A
+ V
B
+ V
C
.
Figure 2-49 Logic diagram of the overvoltage protection for zero sequence voltage
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