Spacelabs qube 91390 - Page 45

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3-3
91390 QUBE
T HEORY
Figure 3-3 FPGA Subsystem
P/O CPU
PCBA
670-1573-xx
SMC1
SMC2
I2C
I2C BUS
I/O
RC RX/TX
SPI
MISC I/O
AUDIO
CODEC
AUDIO
AMP
P070
FPGA
PLD
SPI BUS
11.4MHz
Clock
RKEY
CONTROL
I2C BUS
FPGA PGM
RC RX/TX
MISC I/O
MISC I/O
FPGA PGM
SPI BUS
FROM J50
SDLC CLOCK
TO SDLC SECTION OF CPU
MAIN
SPKR
TO/FROM
MON-DOCK PCBA
P/O CPU