UM0306 Interrupts and events
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Rising Trigger selection register (EXTI_RTSR)
Address Offset: 08h
Reset value: 0000 0000h
Note: The external wake-up lines are edge triggered, no glitches must be generated on these
lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
Falling Trigger selection register (EXTI_FTSR)
Address Offset: 0Ch
Reset value: 0000 0000h
Note: The external wake-up lines are edge triggered, no glitches must be generated on these
lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved TR18 TR17 TR16
rw rw rw
1514131211109 87654321 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0
TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved TR18 TR17 TR16
rw rw rw
1514131211109 87654321 0
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0
TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.