UM0306 Advanced control timer (TIM1)
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12.4.9 Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
● Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIM1_CCMRx register) and the output polarity
(CCxP bit in the TIM1_CCER register). The output pin can keep its level (OCXM=000),
be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on
match.
● Sets a flag in the interrupt status register (CCxIF bit in the TIM1_SR register).
● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIM1_DIER register).
● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIM1_DIER register, CCDS bit in the TIM1_CR2 register for the DMA request
selection).
The TIM1_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIM1_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse Mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIM1_ARR and TIM1_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIM1_CR1 register.
The TIM1_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIM1_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 55.
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