UM0306 Serial peripheral interface (SPI)
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CRC error
This flag is used to verify the validity of the value received when the CRCEN bit in the
SPI_CR1 register is set. In full-duplex mode, the CRCERR flag in the SPI_SR register is set
if the value received in the shift register (after transmission of the transmitter SPI_TXCRCR
value) does not match the receiver SPI_RXCRCR value.
16.3.9 Interrupts
16.4 SPI register description
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
16.4.1 SPI control register 1 (SPI_CR1)
Address Offset: 00h
Reset Value: 0000 0000 (0000h)
Table 48. SPI interrupt requests
Interrupt Event
Event
Flag
Enable
Control
Bit
Transmit buffer empty Flag TXE TXEIE
Receive buffer Not empty Flag RXNE RXNEIE
Master Mode Fault Event MODF
ERRIEOverrun Error OVR
CRC Error Flag CRCERR
1514131211109876543210
BIDI
MODE
BIDI
OE
CRC
EN
CRC
NEXT
DFF
RX
ONLY
SSM SSI
LSB
FIRST
SPE BR [2:0] MSTR CPOL CPHA
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15
BIDIMODE: Bidirectional data mode enable
0: 2-line uni-directional data mode selected
1: 1-line bidirectional data mode selected
Bit 14
BIDIOE: Output enable in bidirectional mode
This bit combined with BIDImode bit selects the direction of transfer in
bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
In master mode, the MOSI pin is used and in slave mode, MISO pin is used.
Bit 13
CRCEN: Hardware CRC calculation enable
0: CRC calculation disabled
1: CRC calculation Enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for
correct operation
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