UM0306 Debug support (DBG)
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20 Debug support (DBG)
20.1 Overview
The STM32F10x is built around a Cortex-M3 core which contains hardware extensions for
advanced debugging features. The debug extensions allow the core to be stopped either on
a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s
internal state and the system’s external state may be examined. Once examination is
complete, the core and the system may be restored and program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32F10x MCU.
Two interfaces for debug are available:
● Serial wire
● JTAG debug port
Figure 184. Block diagram of STM32F10x-level and Cortex-M3-level debug support
Note: The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight
Design Kit.
Cortex-M3
Core
SWJ-DP
AHB-AP
Bridge
NVIC
DWT
FPB
ITM
TPIU
DCode
interface
System
interface
Internal Private
Peripheral Bus (PPB)
External Private
Peripheral Bus (PPB)
Bus Matrix
Data
Trace Port
DBGMCU
STM32F10x debug support
Cortex-M3 debug support
JTMS/
JTDI
JTDO/
JNTRST
JTCK/
SWDIO
SWCLK
TRACESWO
TRACESWO
TRACECK
TRACED[3:0]
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