ST ST32M103 Series - DMA Interrupt Flag Clear Register (DMA

UM0306 DMA controller (DMA)
115/519
7.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address Offset: 04h
Reset Value: 0000 0000 (00h)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CTEIF
7
CHTIF
7
CTCIF
7
CGIF
7
CTEIF
6
CHTIF
6
CTCIF
6
CGIF
6
CTEIF
5
CHTIF
5
CTCIF
5
CGIF
5
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1514131211109876543210
CTEIF
4
CHTIF
4
CTCIF
4
CGIF
4
CTEIF
3
CHTIF
3
CTCIF
3
CGIF
3
CTEIF
2
CHTIF
2
CTCIF
2
CGIF
2
CTEIF
1
CHTIF
1
CTCIF
1
CGIF
1
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Bits 31:28 Reserved, always read as 0.
Bits 27, 23, 19,
15, 11, 7, 3
CTEIFx: Channel x Transfer Error clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18,
14, 10, 6, 2
CHTIFx: Channel x Half Transfer clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17,
13, 9, 5, 1
CTCIFx: Channel x Transfer Complete clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16,
12, 8, 4, 0
CGIFx: Channel x Global interrupt clear (x = 1 ..7)
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
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