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UM0306 Interrupts and events

107/519

Pending register (EXTI_PR)

Address Offset: 14h

Reset value: xxxx xxxxh

6.3.1 EXTI register map

Refer to Table 1 on page 27 for the register boundary addresses.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PR18 PR17 PR16

rc_w1 rc_w1 rc_w1

1514131211109 87654321 0

PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:19 Reserved, must be kept at reset value (0).

Bits 18:0

PRx: Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge

detector.

Note: If an interrupt request occurs one cycle before entering STOP mode, then the

EXTI_PR register will be updated only after exit from STOP mode, generating an

interrupt request if the corresponding bit in the EXTI_IMR register is set

Table 28. External interrupt/event controller register map and reset values

Offset Register

00h

EXTI_IMR

Reserved

MR[18:0]