Interrupts and events UM0306
98/519
6 Interrupts and events
6.1 Nested vectored interrupt controller (NVIC)
Features
● 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3)
● 16 programmable priority levels
● Low-latency exception and interrupt handling
● Power management control
● Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored
Interrupt Controller of the ARM Cortex-M3
TM
Technical Reference Manual.
6.1.1 SysTick calibration value register
The SysTick calibration value is fixed to 9000 which allows the generation of a time base of
1ms with the SysTick clock set to 9 MHz (max HCLK/8).
6.1.2 Interrupt and exception vectors
Table 27. Vector table
Position
Priority
Type of
priority
Acronym Description Address
- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked
to the NMI vector.
0x0000_0008
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018
- - - Reserved
0x0000_001C -
0x0000_002B
3 settable SVCall
System service call via SWI
instruction
0x0000_002C
4 settable Debug Monitor Debug Monitor 0x0000_0030
- - - Reserved 0x0000_0034
5 settable PendSV Pendable request for system service 0x0000_0038
To Next Page
Loading...
Need help?
General
