ST ST32M103 Series User Manual

Advanced control timer (TIM1) UM0306
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12.3 Block diagram
Figure 24. Advanced control timer (TIM1) block diagram
Prescaler
AutoReload Register
COUNTER
Capture/Compare 1 Register
Capture/Compare 2 Register
U
U
U
CC1I
CC2I
ETR
TIM1CLK from RCC
Trigger
Controller
+/-
Stop, Clear or Up/Down
TI1FP1
TI2FP2
from TIM2 (ITR1)
from TIM3 (ITR2)
from TIM4 (ITR3)
TRGI
Controller
Encoder
Interface
Capture/Compare 3 Register
U
CC3I
output
control
DTG
DTG registers
TRGO
OC1REF
OC2REF
OC3REF
REP Register
U
Repetition
counter
UI
Reset, Enable, Up/Down, Count
Capture/Compare 4 Register
U
CC4I
OC4REF
CK_PSC
TI4
Prescaler
Prescaler
IC4PS
IC3PS
IC1
IC2
Prescaler
Prescaler
Input Filter &
EdgeDetector
IC2PS
IC1PS
TI1FP1
output
control
DTG
output
control
DTG
output
control
Reg
event
Notes:
Preload registers transferred
to active registers on U event
according to control bit
interrupt & DMA output
Input Filter
Polarity Selection & Edge
Detector & Prescaler
ETRP
TGI
TRC
TRC
IC3
IC4
ITR
ETRF
TRC
TI1F_ED
Input Filter &
EdgeDetector
Input Filter &
EdgeDetector
Input Filter &
EdgeDetector
CC1I
CC2I
CC3I
CC4I
TI1FP2
TI2FP1
TI2FP2
TI3FP3
TRC
TRC
TI3FP4
TI4FP3
TI4FP4
BI
TI3
TI1
TI2
XOR
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
BRK
TIM1_BKIN
OC1
OC2
OC3
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH3N
OC3N
TIM1_CH2N
OC2N
TIM1_CH1N
OC1N
OC4
TIM1_CH4
TIM1_ETR
to other timers
Mode
Slave
PSC
CNT
Internal Clock (CK_INT)
CK_CNT
ETRF
Clock failure event from clock controller
Polarity Selection
CSS (Clock Security system
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ST ST32M103 Series Specifications

General

Brand	ST
Model	ST32M103 Series
Category	Microcontrollers
Language	English