ST ST32M103 Series - Capture;Compare Register 2 (TIM1_CCR2); Capture;Compare Register 3 (TIM1_CCR3)

Advanced control timer (TIM1) UM0306
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12.5.15 Capture/compare register 2 (TIM1_CCR2)
Address offset: 38h
Reset value: 0000h
12.5.16 Capture/compare register 3 (TIM1_CCR3)
Address offset: 3Ch
Reset value: 0000h
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CCR2[15:0]
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Bits 15:0
CCR2[15:0]: Capture/Compare 2 Value.
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR2
register (bit OC2PE). Else the preload value is copied in the active capture/compare 2
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
1514131211109876543210
CCR3[15:0]
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Bits 15:0
CCR3[15:0]: Capture/Compare Value.
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR3
register (bit OC3PE). Else the preload value is copied in the active capture/compare 3
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signalled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
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