ST ST32M103 Series User Manual

List of figures UM0306
20/519
Figure 49. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 50. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 167
Figure 51. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 52. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 53. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 54. PWM input mode timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 55. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 56. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 57. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 58. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 59. Dead-Time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 175
Figure 60. Dead-Time waveforms with delay greater than the positive pulse.. . . . . . . . . . . . . . . . . . 175
Figure 61. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 62. Clearing TIM1 OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 63. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 64. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 66. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 184
Figure 67. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 68. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 69. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 70. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 71. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 72. General purpose timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 73. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 223
Figure 74. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 224
Figure 75. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 76. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 77. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 78. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 79. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 226
Figure 80. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 227
Figure 81. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 82. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 83. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 84. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 85. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 229
Figure 86. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 230
Figure 87. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 88. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 231
Figure 89. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 90. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 231
Figure 91. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 232
Figure 92. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 93. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 94. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 95. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 96. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 97. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 235
Figure 98. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 99. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 100. PWM input mode timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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ST ST32M103 Series Specifications

General

Brand	ST
Model	ST32M103 Series
Category	Microcontrollers
Language	English