UM0306 Advanced control timer (TIM1)
217/519
Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIM1_BDTR register.
Bit 10
OSSI: Off-State Selection for Idle mode.
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
enable register (TIM1_CCER) on page 209).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as
CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed
(LOCK bits in TIM1_BDTR register).
Bits 9:8
LOCK[1:0]: Lock Configuration.
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIM1_BDTR register, OISx and OISxN bits in
TIM1_CR2 register and BKE/BKP/AOE bits in TIM1_BDTR register can no longer be
written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in
TIM1_CCER register, as long as the related channel is configured in output through
the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIM1_CCMRx registers, as long as the related channel is configured in output
through the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIM1_BDTR
register has been written, their content is frozen until the next reset.
Bits 7:0
DTG[7:0]: Dead-Time Generator set-up.
This bit-field defines the duration of the dead-time inserted between the
complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
dtg
with t
dtg
=t
DTS
.
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
dtg
with T
dtg
=2xt
DTS
.
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=8xt
DTS
.
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
dtg
with T
dtg
=16xt
DTS
.
Example if T
DTS
=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BDTR register).
To Next Page
Loading...
Need help?
General
