UM0306 Memory and bus architecture
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Reading Flash memory
Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
● Latency: Number of wait states for a read operation programmed on-the-fly (from 1 to
7).
● Prefetch: it can be enabled/disabled on-the-fly to optimize CPU execution.
● HalfCycle: for power optimization
Note: 1 These options should be used in accordance with the Flash memory access time.
2 Half cycle configuration is not available in combination with a prescaler on the AHB. The
clock system should be equal to the HCLK clock. This feature can therefore be used only
with a direct clock from 8 MHz RC Oscillator or with the Main Oscillator.
3 Enable and Disable Prefetch modes should be performed when fast clock is disabled (no
Prescaler on AHB)
4 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
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