ST ST32M103 Series - Page 311

UM0306 Controller area network (bxCAN)
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Bit 5
FFIE1: FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 4
FMPIE1: FIFO Message Pending Interrupt Enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Bit 3
FOVIE0: FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 2
FFIE0: FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 1
FMPIE0: FIFO Message Pending Interrupt Enable
0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Bit 0
TMEIE: Transmit Mailbox Empty Interrupt Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Note: refer to Section 14.6: Interrupts.
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