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ST ST32M103 Series User Manual

ST ST32M103 Series
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Inter-integrated circuit (I2C) interface UM0306
342/519
corresponding DMA channel is reached, the DMA controller sends an End of Transfer EOT
signal to the I
2
C interface and generates a Transfer Complete interrupt if enabled:
Master Transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the STOP condition.
Master Receiver: The DMA controller sends a hardware signal EOT_1 corresponding
to the (number of bytes -1). If, in the I2C_CR2 register, the LAST bit is set, I
2
C
automatically sends a NACK after the next byte following EOT_1. The user can
generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
Note: Please refer to the product specs for availability DMA controller. If DMA is not available in
the product, the user should use I
2
C as explained in section 1.4. In the I
2
C ISR, the user can
clear TxE/ RxNE flags to achieve continuous communication.
Transmission using DMA
DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. The DMAEN bit must be set only after receiving the address sequence, when
ADDR is cleared. Data will be loaded from a Memory area configured using the DMA
peripheral (refer to the DMA specification) to the I2C_DR register whenever the TxE bit is
set. To map a DMA channel for I
2
C transmission, perform the following sequence. Here x is
the channel number.
1. Set the I2C_DR register address in the DMA_CPARx
register. The data will
be moved to this address from the memory after each TxE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded into I2C_DR from this memory after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
register. After each TxE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Set the DIR bit and, in the DMA_CCRx register, configure interrupts after half
transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
2
C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITEVTEN bit in the I2C_CR2 register if DMA is used for transmission.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
The DMAEN bit must be set only after receiving the address sequence, when ADDR is
cleared. Data will be loaded from the I2C_DR register to a Memory area configured using
the DMA peripheral (refer to the DMA specification) whenever a data byte is received. To
map a DMA channel for I
2
C reception, perform the following sequence. Here x is the
channel number.
1. Set the I2C_DR register address in DMA_CPARx
register. The data will be
moved from this address to the memory after each RxNE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded from the I2C_DR register to this memory area after each RxNE event.
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ST ST32M103 Series Specifications

General IconGeneral
BrandST
ModelST32M103 Series
CategoryMicrocontrollers
LanguageEnglish

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