Universal synchronous asynchronous receiver transmitter (USART) UM0306
386/519
When a character is received
● The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
● An interrupt is generated if the RXNEIE bit is set.
● The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
● In Multi-buffer, RXNE is set after every byte received and is cleared by the DMA read to
the Data Register.
● In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The
RXNE bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Note: The RE bit should not be reset while receiving data. If the RE bit is disabled during
reception, the reception of the current byte will be aborted.
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the IDLEIE bit is set.
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
● The ORE bit is set.
● The RDR content will not be lost. The previous data is available when a read to
USART_DR is performed.
● The shift register will be overwritten. After that point, any data received during overrun
is lost.
● An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
● The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received. It may also occur when the
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