USB full speed device interface (USB) UM0306
424/519
Note: Due to USB data rate and packet memory interface requirements, the APB1 clock frequency
must be greater than 8 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the register. Each table entry is
associated to an endpoint register and it is composed of four 16-bit words so that table start
address must always be aligned to an 8-byte boundary (the lowest three bits of register are
always “000”). Buffer descriptor table entries are described in the Section 18.6.3: Buffer
descriptor table. If an endpoint is unidirectional and it is neither an Isochronous nor a
double-buffered bulk, only one packet buffer is required (the one related to the supported
transfer direction). Other table locations related to unsupported transfer directions or unused
endpoints, are available to the user. isochronous and double-buffered bulk endpoints have
special handling of packet buffers (Refer to Section 18.5.4: Isochronous transfers and
Section 18.5.3: Double-buffered endpoints respectively). The relationship between buffer
description table entries and packet buffer areas is depicted in Figure 165.
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