Debug support (DBG) UM0306
504/519
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
● In SLEEP mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This will feed HCLK with the same clock that is provided to FCLK
(system clock previously configured by the software).
● In STOP mode, the bit DBG_STOP must be previously set by the debugger. This will
enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.
20.15.2 Debug support for timers and watchdog and bxCAN
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
● they can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
● They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
20.15.3 Debug MCU configuration register
This register allows the configuration of the MCU under DEBUG. This concerns:
● Low-power mode support
● Timer and Watchdog counters support
● bxCAN communication support
● Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042000
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR
Address: 0xE0042004
Only 32-bits access supported
POR Reset: 0x00000000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Res.
DBG_
CAN_
STOP
DBG_
TIM4_
STOP
DBG_
TIM3_
STOP
DBG_
TIM2_
STOP
DBG_
TIM1_
STOP
DBG_
WWDG
_
STOP
DBG_
IWDG
STOP
TRACE_
MODE
[1:0]
TRACE
_
IOEN
Reserved
DBG_
STAND
BY
DBG_
STOP
DBG_
SLEEP
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