Controller Architecture 5
Chapter 1 Theory of Operation
Main Processor Architecture
A controller contains three MPs. Each MP controls a separate channel and operates
in parallel with the other two MPs.
A dedicated I⁄O control processor on each MP manages the data exchanged
between the MP and the I⁄O modules. A triplicated I⁄O bus, located on the
baseplates, extends from one column of I⁄O modules to another column of I⁄O
modules using I⁄O bus cables.
As each input module is polled, the appropriate channel of the I⁄O bus transmits
new input data to its MP. The input data is assembled into a table in the MP and is
stored in memory for use in the voting process.
The individual input table in each MP is transferred to its neighboring MP over the
TriBus. After this transfer, voting takes place. The TriBus uses a programmable
device with direct memory access to synchronize, transmit, and compare data
among the three MPs.
If a disagreement occurs, the signal value found in two of three tables prevails, and
the third table is corrected accordingly. One-time differences which result from
sample timing variations are distinguished from a pattern of differing data. Each
MP maintains data about necessary corrections in local memory. Any disparity is
flagged and used at the end of the scan by the built-in fault analyzer routines to
determine whether a fault exists on a particular module.
The MPs send corrected data to the application. The 32-bit MP executes the
application in parallel with the neighboring MPs and generates a table of output
values that are based on the table of input values according to user-defined
rules.The I⁄O control processor on each MP manages the transmission of output
data to the output modules by means of the I⁄O bus.
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