u-blox ANTARIS 4 - Design-In; Schematic Design-In Checklist for ANTARIS 4


your position is our focus
3 Design-In
swellasReferenceSchematicsfornewdesignswithANTARIS
®
4.For
For Dead Reckoning GPS r to the LEA-4R/TIM-4R System
ThissectionprovidesaDesign-InChecklista
migrationofexistingANTARIS
®
productdesignstoANTARIS
®
4pleaserefertoAppendix D.
a Design-In for for the LEA-4R/TIM-4R  Modules refe
Integration Manual [7].
3.1 Schematic Design-In Checklist for ANTARIS
®
4
Designing-inaTIM-4x,LEA-4xorNEO-4xGPSreceiveriseasyespeciallywhenadesignisbasedonthereference
 ecklist when developing any ANTARIS
®
4 GPS
ave you chosen the optimal module?
heANTARIS
®
4receiverfamilyhasbeenintentionallydesignedtoallowGPSreceiverstobeoptimallytailoredto
tion 2.3).Changingbetweenthedifferentvariantsiseasy(see Section 3.2)
ee Section 1.7 and 4.5.5)?–Thenchooseanxxx-xHorxxx-xSclassreceiver.
settings,youwillhave
Che
Section 4.2.2)

vebatterydrain(see Section 4.2.2).
ationsinSection 4.2.3.
Antenna (see Section 4.3)
 Thetotalnoisefigureshouldbewellbelow3dB.
 Ifapatchantennaisthepreferredantenna,chooseapatchofatleast18x18mm.25x25mmisevenbetter.
 Makesuretheantennaisnotplacedclosetonoisypartsofthecircuitry.(e.g.micro-controller,display,etc.)
 For active antennas add a 10R resistor (see Section 4.3.3.2) in front of V_ANT input for short circuit
protectionorusetheantennasupervisorcircuitry(seeSection 4.3.3.2).
 UseaninductortoprovidetheantennasupplyvoltageforLEA-4MandNEO-4S(sections4.3.3.1and3.6.6).
 FormigrationofANTARIS
®
SupervisorcircuitrytoANTARIS
®
4,reduceR5to33k(Vant=2.6…6.0V)
design in Appendix C. Nonetheless, it pays-off to do a quick sanity check of the design. This section lists the
most important items for a simple design check. The Layout Checklist in
Section 3.4 also helps to avoid an
unnecessaryrespinofthePCBandhelpstoachievethebestpossibleperformance.
Note It’s highly recommended to follow the Design-In Ch
applications.Thismayshortenthetimetomarketandthedevelopmentcostsignificantly.
H
T
specificapplications(see also Sec
 DoyouneedSuperSense(s
 Ifyouwanttobeabletoupgradethefirmwareor topermanentlysaveconfiguration
touseProgrammablereceivermodule?–Thenchooseanxxx-xHorxxx-xPclassreceiver.
ck Power Supply Requirements and Schematic (Section 4.2.1):
 Isthepowersupplywithinthespecifiedrange?
 ArethevoltagesVDDIOandVDDUSBwithinthespecifiedrange?
 PlaceanyLDOasnearaspossibletotheVCCpinofthemodule;ifthisisnotpossibledesignawide power
trackorevenapowerplanetoavoidresistancebetweentheLDO/powersourceandtheGPSModule.
 TherippleonVCC hastobebelow50mVpp?
ttery (seeBackup Ba
 ForachievingaminimalTTFFafterapowerdown,makesuretoconnectabackupbatterytoV_BAT.
Whenyouconnectthebackupbatteryforthefirsttime,makesureVCC isonor– ifnotpossible–powerup
themoduleforashorttime(e.g.1s)ASAPinordertoavoidexcessi
 Whilepoweroff,makesurethereare nopull-upor downresistorsconnectedtothe RxD1,RxD2,EXTINT0
andEXTINT1asthiscouldcausesignificantbackuporsleepcurrent(>25µAormoreinsteadof5µA).Check
ifyoufollowedtherecommend
GPSModules-SystemIntegrationManual(SIM)(incl.ReferenceDesign) Design-In
GPS.G4-MS4-05007-A1
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