u-blox ANTARIS 4 - Layout Design-In Checklist for ANTARIS 4

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sign-In Checklist for ANTARIS
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4
3.5 Layout De
FollowthischecklistforyourLayoutdesigntogetanoptimalGPSperformance.
Layout optimizations (Section 3.6)
 IstheGPSmoduleplacedaccordingtotherecommendationinSection 3.6.2?
theGroundingconcept(seeSection 0)?
ed shielding, add as many vias as poss e micro strip, around the serial
communicationlines,underneaththeGPSmoduleetc.
 Only forLEA-4M andNEO-4S:Has the optional inductorfor the(active) antennabiasvoltage been routed
accordingtotherecommendationinsection3.6.6?
Calculation of the micro strip (Section 3.6.5)
 Themicrostripmustbe50OhmsanditmustberoutedinasectionofthePCBwhereminimalinterference
fromnoisesourcescanbeexpected.
 In case of a multi-layerPCB, use thethickness of thedielectric between the signalandthe 1st GND layer
(typicallythe2ndlayer)forthemicrostripcalculation.
 If thedistancebetween themicro stripandtheadjacentGND area(on thesame layer)doesnotexceed5
timesthetrackwidthofthemicro strip,usethe“CoplanarWaveguide”modelinAppCadtocalculatethe
microstripandnotthe“microstrip”model.
 Haveyoufollowed
 Keepthemicrostripasshortaspossible.
 AddagroundplaneunderneaththeGPSmoduletoreduceinterference.
 For improv ible around th
GPSModules-SystemIntegrationManual(SIM)(incl.ReferenceDesign) Design-In
GPS.G4-MS4-05007-A1
  Page 51