Xerox 560 Reference Manual

2 3 4 Results in R register
o 0 Address in R is an effective virtual address
(address
of a general register).
- 0
o
1
1
Note: Condition code setting 11-- and 1100
--- may be distinguished in the software
by examining the address (bits 10-31).
~1 Access protect code for the page containing
o the memory location specified by the gener-
1 ated address.
Note: This instruction requires two memory references to
the same location for its execution. To preclude
other processors from accessing the effective loca-
tion during this time, the memory unit containing
the effective location is reserved (not accessible to
other processors) until the LRA· instruction is
completed.
LMS
LOAD MEMORY STATUS
(Word index al ignment, privileged)
LOAD MEMORY STATUS is used to determine memory unit
status and/or to perform diagnostic action on a memory unit.
The effective address is used to determine the memory unit.
The condition code setting immediately before execution
determines the diagnostic action to be performed. The ef-
fective address always references memory even if it is less
than 16. The condition code can be set to the desired value
before execution of LMS with the LCF or LCFI instructions.
RegisTer R is loaded with the result of the action. The
condition code is set at the conclusion of execution to
reflect the status of the word loaded (if any).
Affected: (R),CC
T rap:
See liT rap System ",
Chapter 2.
Initial condition code settings:
2 3 4 LMS Action
o 0 0 0 Read and set - causes the same action as the
LOAD AND SET (LAS) instruction, except for·
condition code serrmgs. Normai traps are
allowed including write protect.
000
Read and inhibit parity - loads the effective
word into R. If a memory parity error is de-
tected, the memory does not take a "snapshot 11
or generate a Memory Fau I t Interrupt (MFI).
118 Control Instructions
2 3 4
LMS Action
It does, however, generate the Memory Parity
Error
signal. The basic processor inhibits the
trap that would·ordinarily occur for the mem-
ory parity error.
o 0
o Clear memory - stores zero in the memory
location specified by the address.
o 0 Reserved.
o
o
o
o
o 0
Reserved.
o
Reserved.
o Read
write lock - loads a pair of 4-bit write
locks into byte 3 of R (bits 24-31) and 0 in all
other bit positions of R. The write lock stored
in
bits 24-27 is stored in the memory system's
Write Lock memory at the location correspond-
ing to bits 17-21 of the effective address,
bit 22=0. The write lock stored in bits 28-31
corresponds to bits 17-21 of the effective ad-
dress, bit 22=1.
Write write lock - stores byte 3 of the data
word sent to memory as a pair of write locks
in
the memory system's Write Lock memory at
a location corresponding to bits 17-21 of the
effective address, bit 22= 0 (for data bits 24-27)
and bits 17-21 ofthe effective address, bit 22=1
(for
data bits 28-31).
o 0 0 Read status word ot - loads status word 0 into
R (see Table 9).
o
0 Reserved.
o
0 Read status word 1t - loads status word 1 into
R (see
Table 10).
o Reserved.
o
0 Read status word 0 and clear.
o
Reserved.
o
Write double error - stores an arbitrary word
into a specified memory location, with two
differences compared to a normal Write Word
instruction: (1) Byte 3 in memory is forced to
zero; (2) the arbitrary word is stored in memory
with an intentional wrong parity; on a sUb-
sequent read of that word, the memory issues
the parity error-signal.
Reserved.
Condition code settings after execution.
t Primarily of diagnostic concern.

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