level within the interrupt system (location X
'
5C)
is armed,
enabled,
and not
inhibited,
the request wi
II
be processed
by
the
BP
in
accordance
with the priority
that
prevails
within the interrupt system, the lOPs, and the
I/O
sub-
channels
within
an MIOP.
The
occurrence
of
an
I/O
interrupt because
of
a Stop command is reported as status
information
(bit
position 7 of register
R)
when
the
BP
executes
an
AIO
instruction (normally
part
of
an
I/O
handling routine).
Bi
t posi ti ons
1-7
must be coded as zeros.
Bi
t posi ti ons 8-31
and 40-63
are
ignored; but
it
is recommended
that
they also
be coded as zeros.
Bit
positions
32-39
are devi
ce
depen-
dent
and must be coded as specified in the appropriate
pe-
ripheral
reference
manual.
The Stop command is primari
Iy
used to terminate a command
chain for an unbuffered
device,
as
illustrated
in the first
example given for the Transfer in Channel command.
Note
that
not
all
devices
recognize
the Stop order.
I/O
OPERATION
PHASES
This section describes the
genera
I sequence
of
events (or
phases) of
any
I/O
operati on performed by
an
lOP,
the
function performed by
the
BP,
lOP,
and
device
controller/
device
during
each
phase, and a description of
each
type
of
I/O
operation
including the
applicability
of parameters
that
may be
contained
within a typical operational lOCO.
For
explanation
purposes,
each
I/O
operation has five
ma-
jor phases:
preparation,
initiation,
fetching,
executing,
and termination phase. Each phase is further described
below.
PREPARATION
PHASE
Before
an
I/O
operation may be performed by
an
lOP,
an
appropriate
command list must reside in main memory.
INITIATION
PHASE
Assuming
that
an appropriate command list resides in main
memory,
an
I/O
operation is
initiated
only if the
BP
ex-
ecutes
an
SIO instruction
that
is
accepted
by the addressed
lOP,
device
controller, and
device.
The
acceptance
or
rejection
of
an
SIO
instruction is
contingent
upon
condi-
tions within the addressed lOP,
device
controller,
and
device
and
is
indicated
by the condition codes
at
the com-
pietion of
the
SIO
instruction. in
either
case,
the
BP
is
able
to perform
other
instructions or tasks immediately
after
executing
an
S10
instruction. (Refer to "SIO" instruction,
Chapter
3,
for further detai
Is.
)
A successfu
I
510
i nstructi
on
causes the addressed devi
ce
to
go from the
"ready" condition to the "busy" condition.
148
I/O
Operation
Phases
FETCHING
PHASE
Although
the
services of the
BP
are
not required during
this phase, the
BP
may
at
any time
execute
either
a TIO,
TDV,
or
POL
instruction without interfering with
the
I/O
operation. However, excessive TIOs and
TDVs
may
cause
a
data
overrun condition. The
BP
may also
execute
either
an HIO or
RIO
instruction and stop the
I/O
operation.
(An
HIO may leave the
device
in an unpredictable state; an
RIO
resets
all
controllers and
devices
on the addressed lOP. )
As
a result
of
accepting
an SIO instruction, a command
ad-
dress register within the
I/o
subchannel (assigned to
con-
trol the addressed
device
controller/device)
is
loaded with
the first command doubleword address,
the
content
of
Gen-
eral Register 0 when
the
510
instruction is
accepted.
At
the
appropriate time, as determined by the priority, the
device
controller/device
wi
II
request
that
the
lOP
access
main memory and fetch the first word
of
the lOCO
from
an
even
memory word location and increment the command
address register by one.
The
disposition
of
the first word
is
dependent
upon the contents
of
the first word.
If
the order field contains an
I/o
order for a
device
controller/device,
the
content
of
the order field is
either
loaded into an order register within
the
appropriate
device
controller/device
or
ignored (if the lOCO
is
being fetched
for a
data
chained operation). If the order
is
a Read Back-
ward order, a control flag is also
set
within the
lOP
which
allows the memory byte address to be decremented rather
than incremented during the
data
transfer.
For all orders (excluding the Transfer in Channel command,
described below), the contents
of
bit
positions 10-31 of the
first word is loaded into a memory byte address register
of
an appropriate
I/o
subchannel. Depending upon the
I/O
order, as described under "Execution Phase", the
content
of
the memory byte address register may be used or ignored.
If
used,
it
specifies which memory word location is to be
ac-
cessed and also the number
of
bytes of
data
{or
control
in-
formation} to be transferred into or
out
of
that
location.
If
the
order field contains a Transfer
in
Channel command,
it
is recognized and
executed
immediately by the
lOP.
The
content
of
bit positions
13=31
(designated as,the IInext
com-=
mand doubleword address" field) is loaded
directly
into the
command address register.
The
Transfer in Channel
com-
mand
is
recognized and
executed
by the
lOP,
it
is fetched
and
executed
as
the
result of fetching one word (rather than
two), and
it
is transparent to
the
device
controller/device
(that
is,
it
is
executed
without
affecting
the
continuity of
an
order
that
is
data
chained
or an
I/o
operation
that
is
command
chained).
Note: Although bit positions
0-3
and
8-12
are
currently ignored,
it
is recommended
that
they
be coded
as
zeros.
Immediately
after
executing a Transfer
in
Channel command,
the
iOP
wiii
automaticaiiy
fetch the first word or the next
lOCO as specified by the contents of the "next command
doublewordaddress"
field.
If
the order field
ofthe
next
lOCO
also contains a Transfer
in
Channel command, the
I/o
opera-
tion
is
terminated immediately
and
the lOP enters a Halt state
because an
lOP
control error (IOPCE) occurred (attempting
to
execute
two successive Transfer
in
Channel commands).
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