When
the
CCP/SCSR switch is in
the
CCP position and
switch
0 is in the
IrO"
position, switches 3 through 7
specify
the
binary address of
the
cabinet
whose
Read
Direct
Mode 9
Status Register is to
be
displayed by the 32 panel
indicators.
When
the
CCP/SCSR switch IS
In
the
CCP position and
switch
0 is in the
II
111
position,
switches3
through 7 specify
the
binary address of
the
cabinet
whose
16-bit
Configura-
tion Status Register is
to
be displayed by
the
16 lower-order
indicators.
SINGLE CLOCK
ENABLE
This switch stops all
central
system
clocks
in
the
same
manner as
the
ZCCLK
command. Activating this switch
when
the
basic processor
is
performing normal
data
processing
may
have
an
adverse
effect
on
any
active
I/O
operations.
To
prevent
inadvertent
activation
of this
control,
it
is
disabled
unless the MAINT MODE switch is in
the
ON
position.
SINGLE
CLOCK
STEP
This switch is
active
only when in
Single
Clock
Mode or
when
the
Single Clock Enable switch is
active.
When
active,
this switch causes one system
clock
to be issued
each
time
it
is
placed
in the
STEP
position. The new
single
clock
status, as
selected
by
the
MODE and
SELECT
switches, may be monitored
via
the
32 binary indicators
on
the
System Control Panel; no display is
generated
on the
System Control Console by
activation
of the SCP Single
Clock
Step switch.
OPERATING
PROCEDURES
AND
INFORMATION
This
section
contains
reference
information which may be
required
by
either
the operator or
maintenance/diagnostic
personnel.
LOAD
OPERA
nON
DETAILS
The first
executed
instruction of
the
bootstrap program (in
location
X'26
1
)
loads general register 0 with
the
address of
the
first
I/O
command doubleword (lOCD). The
I/o
address
for
the
SIO
instruction in
location
X
'
27
1
is the
13
low-order
bits of
location
X
'
25
1
(which have been set equal
to
the
load
una
address
asaresu!tofthe
NORMAL
lOAD,
ZCLDN####,
command). During
execution
of
the
SIO
instruction,
gen-
eral
register 0 points
to
locations X
'
20
'
and
X
'
21
1
as
the
first
10CD
for
the
selected
device.
This IOCD
contains
an
order
to
the
selected
peripheral
device
to
read 88
(X
'
58
1
)
bytes of
data
into
consecutive
memory locations beginning
at
word
location
X'2A'
(byte
location
X'A8
1
).
At
the
end
164
Control Commands
of
the
Read
operation,
neither
data
chaining
nor command
chaining
is
called
for in
the
10CD.
The Suppress
Incorrect
Length
(SIL)
flag is set
to
1 so
that
an
incorrect
length
in-
dication
will not
cause
a Transmission Error Halt. After
the
SIO
instruction has
been
executed,
the
basic processor
executes
a
no
instruction with
the
same
effective
address as
the
SIO
instruction. The
no
instruction is
coded
to
accept
only
condition
code
data
from
the
lOP.
The
BCS
instruction (in
location
X'29
1
)
will
cause
a branch
to
X
'
22
1
(a LOAD
IMMEDIATE
instruction), if
either
CCl
or CC2
is
set
to
1.
Execution of the LOAD
IMMEDIATE
instruction
at
X'22'
loads a
count
of
XI
10029
1
into
general register
1.
The
fol-
lowing
BDR
instruction
at
location
X
'
23
1
uses this as a
"delay"
count
before
executing
the
BCR
instruction in
lo-
cation
X'241, which
unconditionally
branches
to
the
TIO
instruction in
location
X'28
1
.
In
normal operations,
CCl
is
reset
to
0 and CC2 remains set
to
1 unti I the
device
can
accept
another
SIO
instruction. At
that
time, the next
instruction is
taken
from
location
X'2A'.
If a Transmission Error or equipment malfunction is
detected
by
either
the
device
or
the
lOP,
the
lOP
instructs
the
device
to
halt
and
to
initiate
an
II
unusual end" interrupt
signal (as
specified
by
appropriate
flags in
the
IOCD,
de-
scribed in
Chapter
4).
The
II
unusual end" interrupt will
be
ignored since
all
interrupt levels have been Disarmed
and
Disabled by the system reset during
the
load
sequence.
The
device
will not
accept
another
SIO
while
the
interrupt
is pending
and
the
BCS
instruction in
location
X
'
29
1
will
continue
to
branch
to
location
X'221. The
correct
operator
action
at
this
point
is
to
repeat
the
NORMAL LOAD,
ZCLDN####, command.
If
there
is no
I/O
address
recog-
nition of
the
load
unit,
the
SIO
instruction
wi
II
not
cause
any
I/O
acti
on
and
CC 1
wi
II
conti nue
to
be
set
to
1 by
the
SIO
and
no
instructions causing
the
BCS
instruction to
branch.
FETCHING and
STORING
DATA
The following examples
illustrate
how diagnostic control
(P-Mode) commands may be used
to
di
splay and al ter
the
contents
of specified memory locations ond control reg! sters
within
the
system. Control commands, as
entered
from a
keyboard
device
functioning as
the
System Control
Con-
sole,
are
shown in the first column. The resulting printouts
are
shown in
the
second column. The third column of
in-
formation is
an
explanation
of
the
functions performed
by
the
different control commands.
Input
Printout
Function
pc
O:DDDDDDDD
@ 80000000
Enter P-Mode
of
operations; contents
of
Q n:gister 0 is
normally displayed.
100/
100/
Select
and
display
O:DDDDDDDD
@ 00000100
contents
of memory
location
X'lOO'.
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