Xerox 560

subroutine. However, with certain classes of errors, if a
second error occurs
while the basic processor is attempting
to recover from the first error, unpredictable results occur.
Inc I uded in th is c lass of traps are the hardware error trap,
some cases of the instruction exception trap, and the watch-
dog timer runout trap. Upon the first occurrence of this
type of trap, the PDF flag is set.
When the PDF flag is set, the processor fault interrupt, the
memory fault interrupt, and count pulse interrupts are auto-
matically inhibited. The other interrupts mayor may not
be inhibited as specified by the program status words, which
are loaded when the trap entry XPSD or PSS is executed.
The PDF flag is normally reset by the last instruction of a
trap routine, which is an LPSD or PLS instruction having
bit 10 equal to 0 and bit 11 equal to 1.
If a second PDF is detected before the PDF flag is reset, the
basic processor "hangs Up" unti I the PDF flag is reset either
by the operator entering the command for RESET BASIC
PROCESSOR or RESET SYSTEM on the operator1s console.
This reset wi II cause the following actions:
1. The processor fault status register is cleared.
2. The PDF flag is cleared and the processor fault inter-
rupt generated flag is cleared.
3. The PSWs are cleared to zero except that the instruc-
tion address is set to location X 126
1
•
4. The basic processor will begin execution with the in-
struction contained in location X126
1
.
REGISTER ALTERED BIT
Complete recoverability after a trap may require that no
main memory
location, no fast memory register, and no
part (or flags) of the PSWs be changed when the trap occurs.
If any of these registers or flags are changed, the Register
Altered bit (60) of the old PSWs is set to 1 and is saved by
the trap XPSD.
Changes to CC1-CC4 cause the Register Altered bit to be
set only if the instruction requires these condition code bits
as subsequent inputs.
Traps caused by conditions detected during operand fetch
and store memory cycles, such as nonexistent memory, ac-
cess protection violation, and memory parity error mayor
may not leave registers, memory, and PSWs unchanged, de-
pending on when they occur during instruction execution.
Generally, these traps are recoverable. This is done by
checking for protection violations and nonexistent memory
at the beginning of execution in case of a multiple operand
access instruction, restoring the original register contents
if execution cannot be completed because of a trap, and
not loading the first word of the PSWs until a possible trap
condition due to access of the second word could have been
detected. Table 5 contains a list of instructions and indi-
cates for these instructions what registers, memory locations,
and bits of the PSWs, if any, have been changed when a
trap
due to an operand access memory cycle occurs.
Tabie 5. RegiSTers Changed aT Time or a Trap Due TO an Operand Access
Instructi ons
Changes
AI, CI, LCFI, LI, MI
Immediate
type, no operand access.
CALl-CAL4, SF,S, WAIT, RD, WD, RIO, No operand access.
POLR, POLP, DSA
LRA Has operand access but traps are suppressed; register bits and
condition codes are set instead.
LB, LCF, LRP, CB No operand store, registers and PSWs unchanged when trap
LH, LAH, LCH, AH, SH, MH, DH, CH due to operand fetch.
CCl-4 may be changed but are not
LW, LAW, LCW, AW, SW, MW, OW, CW
used as input
to any of these instructions.
LD, LAD, LCD, AD, SO, CD, CLM, CLR Registers and memory are preserved, condition codes may be
EaR, OR, AND, LS, INT, CS changed but are not used as input to these instructions.
FAS, FSS, FMS, FDS, FAL, FSL, FML, FDL
AWM, XW, STS, MTB, MTH,
MTW
Memory will be altered and the Register Altered bit set.
STB, STCF, 5TH, STW,
LAS
EXU, BCR, BCS
If the branch condition is true (always for EXU and BAL) and
BAL, BDR, BIR a trap occurs due to access of the indirect address or of the
next (branched to or executed) instruction, the register used
is left unchanged and the program address saved in the PSWs
is the address of the branch or execute instruction.
Trap System 45