to as conversion values. The intermediate results
of
these
instructions
are
accumulated
in internal
basic
processor
registers unti I the instruction is completed; the result is
then loaded
into
the
appropriate
general
register.
Both
instructions use a
counter
(n)
that
is
set
to 0
at
the
beginning
of
the
instruction
execution
and
is incremented by 1 with
each
iteration,
until a total
of
32
iterations
has been
performed.
If a memory
parity
or
protection violation trap occurs
dur-
ing the
execution
of
either
instruction,
the
instruction
se-
quence
is
aborted
(without having
changed
the contents
of
register R
or
Rul) and may be restarted (at the beginning
of
the instruction
sequence)
after
the trap routine
is
processed.
eVA
CONVERT
BY
ADDITION
(yVord
index
alignment)
CONVERT
BY
ADDITION
initially
clears
the internal A
reg-
ister and sets an
internal
counter
(n)
to
O.
If
bit
position n
of
register
Rul
contains a 1, CVA adds the nth conversion
value
(contents
of
the
word location pointed to by the
ef-
fective
address plus
n)
to the
contents
of
the A register,
accumulates
the
sum
in
the
A register, and increments n
by 1. If
bit
position n
of
register
Ru
1
contains
a 0, CVA
only increments n.
If
n is less than
32
after
being
incre-
mented, the
next
bit
position
of
register Rul is examined,
and
the
addition
process continues through n
equal
to 31;
the resu
It
is then loaded
into
register
R.
If, on
any
itera-
tion,
the
sum
has
exceeded
the
value
2
32
-
1
,
CCl
is
set
to 1 i otherwise,
CCl
is
reset to
O.
Affected:
(R),
CC1, CC3,
CC4
O-A,O-n
If (Rul) =1, then
(EWL
+ n) +
(A)
-A,
n + 1 - n
n
If (Run =0. then n +
1-
n
,
'n
'
If
n <
32,
repeat;
otherwise,
(A)
- R and continue to
next
instruction.
Condition
code
settings:
o
2 3 4
Resu
It in R
- 0 0 Zero.
- 0 Bit 0
of
register R is a 1.
OBit
0
of
register R is a 0 and
bit
positions 1-31
of
register R contain
at
least one 1.
- -
Sum
is
correct
(less than
~2).
- -
Sum
is
greater
than 2
32
_1.
74
Floating-Point
Arithmetic Instructions
evs
CONVERT
BY
SUBTRACTION
(yVord
index
alignment)
CONVERT
BY
SUBTRACTION loads the internal A register
with the
contents
of
register
R,
clears
the internal B
regis-
ter,
and sets an internal
counter
(n) to
O.
All conversion
values
are
considered to be
32-bit
positive
quantities.
If
the nth conversion
value
(the contents
of
the
word location
pointed to by the
effective
address plus n)
is
equal to or
less than the
current
contents
of
the A register, CVS
incre-
ments n by 1, adds the two's complement
of
the nth
con-
version
value
to the contents
of
the A register, stores the
sum
in the A regi ster, and stores
ali
n
bi
t position n
of
the
B register. If the nth conversion value is
greater
than the
current
contents
of
the A register,
CVS
only
increments n
by 1. If n
is
less than 32
after
being incremented, the
next
conversion value is compared and
the
process
con-
tinues through n
equal
to 31; the remainder in the A
reg-
ister is loaded into register
R,
and the
converted
quantity
in the B register is loaded into register
Ru1.
Affected:
(R),
(Rul), CC3, CC4
(R)-A,
O-B,
O-n
If
(EWL
+ n) $
(A)
then A -
(EWL
+ n)
-A,
l-B
,n
+
l-n
n
If
(EWL
+ n) >
(A)
then n +
1-
n
If
n <
32,
repeat;
otherwise,
(A)
-
R,
(B)
-
Ru1
and
continue
to the
next
instruction.
Condition
code
settings:
2 3 4 Result in
Rul
- 0 0 Zero.
o
Bit
0
of
register
Ru
i is a L
o
BitOofregisterRu1
is
a 0 and
bit
posi-
tions 1-31 of register
Ru
1 contain
at
least
one
1.
FLOATING-POINT
ARITHMETIC
INSTRUCTIONS
The
floating-point
arithmetic
instructions
are:
Instruction
f'~amc
~,~ncmon;c
Floating Add Short
FAS
Floating Add
Long
FAL
Floating Subtract Short
FSS
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