EasyManua.ls Logo

Xerox 560

Xerox 560
206 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
READ
INTERRUPT
INHIBITS
The following
configuration
of
RD
can be used to
read
the
contents
of
the
interrupt
inhibit
field:
If
the
R field
of
RD
is
nonzero,
the
contents
of
the
interrupt
inhibit
field (bits
37,
38,
39)
of
the
program status words
are
transferred
to
the
least
significant
3 bits
of
the
spe-
cified
R
register
(bits
29,
30,
31).
The
remainder
of
the
R
register
(bits
0-28)
is
cleared
to
zeros.
Affected:
(R)
(PSWs)37_39 - R
29
-
31
0-
R
O
-
28
Note
that
a copy
of
the
interrupt
inhibits
is
retained
in
the
Interrupt Status Register in
the
Processor
Interface
associated
with
each
basic
processor.
LOAD FROM LOW MAIN MEMORY
1*
I 6C I R I X
I~):;
0000Rff~o~~c1~fJ~~~~~~es;~~~
I
o 1 2
31456718910
11112
13
14';5116
17 18
19120212223124252627128
29
30
31
The instruction
allows
reading
the
contents
of
real
memory
locations
0-31
(locations
0-15
shadowed by
the
genera
I
purpose registers). This
allows
access
to
the
Status
Stack
Pointer Doubleword in
locations
0-1
and
the
default
Pro-
gram Status Words (Interrupt
Stack
is
empty) in
locations
2-4.
If
the
R
field
is
nonzero,
the
contents
of
the
main memory
location
identified
by bits 27-31
are
loaded
into
R.
Affected:
(R)
EW-R
READ
INTERNAL
CONTROL
REGISTERS
The following
configuration
of
RD
is
used to
read
the
con-
tents
of
internal
control
(or
Q) registers:
II
I I I i
Rtfe[eDOr
Ad~fe~s
~
* 6C R
X~)~
0000 0011 }}}t@ Q
add
o 1 2
314
5 6 7 8 9
10
1112
13
14
';516
17 18
19
~
21
22 23
'24--2';"26
27 28 29
30
31
If
the
R
field
of
the
RD
instruction
is
nonzerO,
the
contents
of
the
internal
control
register,
as
specified
by
the
IIQ
Ad-
dress" field
of
the
rnstruction (bit positions
27-31),
are
loaded
into
register
R.
Although
the
Q address field permits
any
of
32
addresses to be
specified,
only
the
following may
be
used:
Q Address
Contents
X'lD'
X'lP
{
(Bits
0-13)
- Reserved
(Bits 14-31) -
"Branch from" Program
Counter
{
(Bits
0-7)
- Reserved
(Bits
8-31)
- Load
Device
Address
All
other
Q addresses from
X'OO'
-
X'lF'
are
reserved.
Affected:
(R)
EW-R
READ
DIRECT,
INTERRUPT
CONTROL
(MODE
1)
The following
configuration
of
RD
is
used to control
the
sensing
of
the
various
states
of
the
individual
interrupt
levels
within
the
basi c processor
interrupt
system:
Bits 28 through
31
of
the
effective
address
specify
the
iden-
tification
number
of
the
group
of
interrupt
levels
to
be
con-
trolled
by
the
READ
DIRECT
instruction.
The R
field
of
the
RD
instruction
specifies
a
general
register
that
will
contain
the
bits sensed from
the
individual
inter-
rupt
levels
within
a
specified
group.
For
external
interrupt
groups,
bit
position
16
of
register
R
contains
the
appropriate
indicator
bit
for
the
highest
priority
(lowest number)
inter-
rupt
level
within
the
group
and
bit
position
31
of
register
R
contains
the
indi
cator
bit
for
the
lowest
priority
interrupt
level
within
the
group.
For assignments in
Group
X'O',
see
Table
11. Each
interrupt
level
in
the
designated
group is
sensed
according
to
the
function
code
specified
by bits
21
through 23
of
the
effective
address
of
RD.
The codes and
their
associated
functions
are
as
fol lows:
Code
001
010
Function
Read Armed
or
Waiting
State.
Set
to 1
the
bits in
the
selected
register
which
correspond to
interrupt
levels
in this group
that
are
in
either
the
armed
or
the
waiting
state.
Reset
all
other
bits to
zero.
Read
Waiting
or
Active
State.
Set
to
1
the
bits
in
the
selected
register
which correspond to
each
interrupt
level
in this group
that
is
in
either
the
waiting
or
the
active
state.
Reset
all
other
bits
to
zero.
100 Read Enabled.
Set
to
1
the
bits in
the
selected
register
which correspond
to
each
interrupt
level
in
this
group which
is
enabled.
Reset
all
other
bits
to
zero.
Control Instructions
121

Table of Contents

Other manuals for Xerox 560

Preview: User Guide
User Guide346 pages

Related product manuals