Xerox 560 Reference Manual

next sequential register after register 15 is register 0). The
number of registers to be stored is determined by the value
of the condition code immedi ate Iy before execution of STM.
(The condition code can be set to the desired value before
execution of STM with LCF or LCFI.) An initial value
of 0000 for the condition code causes 16 general registers
to be stored.
Affected: (EWL) to (EWL +CC-1)
(R)-EWL, (R+1)-EWL+1, ... , (R+CC-1)-EWL+CC-1
The STM instruction may cause a trap if its operation ex-
tends into a page of memory that is protected by the access
protection codes or the write locks. A trap may also occur
if the operation extends into a nonexistent memory region.
If the effective virtual address of the STM instruction is in
the range 0 through 15, then the registers indicated by the
R field of the STM instruction are stored in the general reg-
isters rather than main memory. In this case, the results
will be unpredictable if any of the source registers are also
used as destination registers.
STCF STORE CONDITIONS AND FLOATING
CONTROL
(Byte index alignment)
STORE CONDITIONS AND FLOATING CONTROL stores
the current condition code and the current value of the
floating round (FR), floating significance (FS), floating
zero (FZ), and floating normalize (FN) mode control bits
of the program status words into the effective byte location
as fo lIows:
Affected: (EBL)
(PSWs)0_7 -EBL
ANAL YZEjlNTERPRET INSTRUCTIONS
ANLZ ANALYZE
(Word
index alignment)
ANALYZE evaluates the effective word as an instruction.
The ANALYZE instruction always sets the condition codes
to indicate the addressing type of the analyzed instruction
(see condition code settings and Table 6). Except when
Table 6. ANALYZE Table for Operation Codes
X'n'
X'OO'+n
X'20'+n
X'40'+n
X'60'+n
00
-
AI
TTBS
CBS
01
- CI
TBS tt
MBS
02
LCFI ®tt
LI
-CD
-
03
- MI
-
EBS
04
CAll
SF
ANLZ
BDR
05
CAL2
S
CS
BIR
06
CAL3 LAS XW
AWM
07
CAL4
-
STS
EXU
08
PLW
CYS
EOR
BCR
09 PSW
CYA tt
OR
BCS
OA PLM
LM@
LS
BAL
OB
PSM
STM
AND
INT
OC
PLS
t
LRAt SlOt
RDt
OD
psst LMst
TIot
WDt
OE
LPSDt@tt
WAITt
TDyt
AIOt
OF
XPSD
t
LRPt
HIOt
MMC
t
10
AD
SW
AH LCF
11
CD CW
CH CB
12
LD LW LH
LB
13
MSP
MTW
MTH
MTB
14
-
LYAW -
STCF
15
STD STW
STH STB
16
-
DW
nl-l(A)tt
PArI( (ffitt
- .. ~
. - -- .. '-.::/
17
-
MW
MH UNPK
18
SD SW
SH
DS
19 CLM
CLR
-
DA
1A
LCD
LCW
LCH
DD
1B
LAD LAW LAH
DM
1C FSL
FSS
-
DSA
1D FAL
FAS
-
DC
1E
FDL
FDS
-
DL
1F FML
FMS
- DST
tPrivileged instructions.
tt Decimal value of condition code settings when an-
alyzed instruction calls for direct addressing.
If an-
alyzed instruction calls for indirect addressing, add 2
to
the value shown.
the analyzed instruction is an immediate operand in-
struction, an effective virtual address for the analyzed
instruction is also calculated and loaded into register R.
Analyze/Interpret Instructions 57

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