Xerox 560

If characteristic overflow occurs, the basic processor always
traps to location X
'
44
1
with the general registers unchanged
and the condition code set to 0110 if the result is positive,
or to 0101 if the result is negative.
FLOATING-POINT MULTIPLY AND DIVIDE
The floating round (FR) and floating zero (FZ) mode con-
trol bits determine the operation of floating-point multi-
plication and division (if characteristic overflow does not
occur and division by zero is not attempted) as follows:
FR Floating round:
FR = 0 No roundi ng speci fi ed.
FR = 1 The results of floating multiplication and
division instructions are to be rounded. For
multiply or divide operations, a normalized
product or quotient is produced, appended
by a guard digit. This wi II be an absolute
value.
Note: The example above (under "Floating-Point
Add and Subtract") is not possible for multiply
and divide. Therefore, there is never a time
penalty for rounding.
FZ
Floating zero:
FZ = 0 If the final result of a multiplication or divi-
sion operation cannot be expressed in normal-
ized form because of the characteristic being
reduced below zero, underflow has occurred.
If underflow occurs, the result is set equal to
"true" zero and the condition code is set to
1100. If underflow does
not occur, the
condition code is set to 0010 if the result is
pbsitive, to 0001 if the resulT is negutive, or
to 0000 if the result is zero.
FZ = 1 Underflow causes the basic processor to trap
to location X
'
44
1
with the contents of the
general registers unchanged. The condition
code is set to 1110 if the result is positive,
or to 1101 if the result is negative. If under-
flow does not occur, the resultant action is
the same as that for FZ = O.
If the divisor is zero in a floating-point division; the basic
processor always traps to location X
'
44
1
with the general
registers unchanged and the condition code set to 0100. If
characteristic overflow occurs, the basic processor always
traps to location X'44' with the general registers unchanged
and the condition code set to 0110 if the result is positive,
or to 0101 if the result is negative.
78 Floating-Point Arithmeti c Instructions
CONDITION CODES FOR
FLOATING-POINT INSTRUCTIONS
The condition code settings for floating-point instructions
are summarized in Table 8. The following provisions apply
to all floating-point instructions:
1. Undeflow
and overflow detection apply to the final
characteristic, not to any "intermediate" value.
2. If a floating-point operation results in a trap, the origi-
na contents of all general registers remain unchanged.
3. All shifting, truncation, and rounding are performed
on
absolute magnitudes. If the fraction is negative,
then the two's complement is formed after shifting or
truncation.
FAS FLOATING ADD SHORT
0Nord
index alignment)
The effective word and the contents of register R are loaded
into a set of internal registers and a low-order hexadecimal
zero (guard digit) is appended to both fractions, extending
them to seven hexadecimal digits each. FAS then forms the
floating-point sum of the two numbers. (See "FR Floating
round" under "Floating-Point Add and Subtract", if round-
ing applies.) If no floating-point arithmetic fault occurs,
the sum is loaded into register R as a short-format floating-
point number.
Affected: (R), CC
(R) + EW-R
Trap: Floating-point arith-
metic fault
FAL FLOATING ADD LONG
(Doubleword index alignment)
The effective doubleword and contents of registers Rand Ru1
are loaded into a set of internal registers.
The
operation of FAL is identical to that of FLOATING
ADD
SHORT (FAS) except that the fractions to be added
are each 14 hexadecimal digits long, guard digits are ap-
pended to the fractions only if rounding is specified, and R
must
he an even value for correct results. If no flooting-
point arithmetic fault occurs, the sum is loaded into regis-
ters Rand Ru 1 as a long-format floating-point number.
Affected: (R), (Rul), CC
(R, Rul) + ED - R, Rul
Trap: Floating-point arith-
meti c fault, instruc-
tion exception