Xerox 560 Reference Manual

retry only for hardware errors that would otherwise result
in a basic processor trap to location X
I
4C. Automatic in-
struction retry is inhibited if:
1 • The current instruction is being executed as a trap or
interrupt instruction;
2. The Register Altered bit (bit position 60) of the current
PSWs is set to 1 at the time of detection of the
hardware error; or
3. The Retry Inhibit bit (bit position 0) in the basic pro-
cessor control register is set to 1.
INSTRUCTION EXCEPTION TRAP
The instruction exception trap occurs whenever the basic
processor detects a set of operations that are called for in
an instruction but cannot be executed because of either a
hardware restriction or a previous event.
The different conditions that cause the instruction exception
trap are:
1. A processor-detected fau It that occurs during the ex-
ecution of an interrupt or trap entry sequence. An
interrupt or trap entry sequence is defined as the se-
quence of events that consists of: (a) initiating an
interrupt or trap; (b) accessing the instruction in the
interrupt or trap location; and (c) executing that in-
struction, including the exchange of the program
status words, if required. Note that instructions ex-
ecuted as a result of the interrupt or trap location are
not considered part of the entry sequence.
2. An illegal instruction is found in the trap (not XPSD or
PSS) or interrupt (not XPSD, PSS, MTB, MTH, MTW) lo-
cation when executing a trap or interrupt sequence.
3. Bit positions 12-14 of the MOVE TO MEMORY CON-
TROL (MMC) instruction are interpreted as an illegal
configuration. This is, any configuration other than
100, 010, 101, 001, or 011 •
4. The set of operations, primarily doubleword and byte-
string instructions, that yield an unpredictable result
when an incorrect register is specified; this type of
fault is called "invalid register designation II and in-
cludes the following instructions
ll
• t
Register
0 Specified
Edit Byte String (EBS)
Odd Register Specified
Add Doub I ewo rd (A D)
Subtract Doubleword (SD)
tliInvalid register designation II faults do not set the PDF
flag.
44 Trap System
Floating Add
Long (FAL)
Floating Subtract Long (FSL)
Floating Multiply Long (FML)
Floating Divide Long (FDL)
Translate Byte String (TBS)
Translate and Test Byte String (TTBS)
Edit Byte String (EBS)
Move to Memory Control (MMC)
TRAP CONDITION CODE
The Trap Condition Code (TCC) differentiates between the
different fault types. Table 4 shows the settings of the TCC
for the various faults that may be detected during a trap or
interrupt entry sequence.
Table 4. TCC Setting for Instruction Exception
Trap
X
I
4D
1
Fault Type
TCC
Trap or interrupt sequence and
1 1 1
pro~essor-detected fault.
Trap or interrupt sequence with 1 1
0
invalid instruction.
MMC configuration invalid.
0
0
1
Invalid
register designation.
0
0
0
POWER ON TRAP
1
0
0
1
Power On causes the basic processor to reset and then trap
tolocationX
I
50
I
•
This will occur only following restoration
of power after an interruption of less than 500 milliseconds.
POWER OFF TRAP
Power Off occurs at interruptible point. As source power is
going
off, the basic processor traps to location X 1511 and
allows sufficient time for storage of information before the
system becomes inoperable.
PROCESSOR DETECTED fAULT fL~G
The Processor Detected Fault (PDF) flag aids in solving a
multiple error problem. Most traps occur because of a dy-
namic programming consideration (i.e., overflow, attempted
division by zero, incorrect use of an instruction or address,
etc.) and recovery is easi Iy handled by another software

Xerox 560 Specifications

General

Print Resolution	2400 x 2400 dpi
Monthly Duty Cycle	Up to 300, 000 pages
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Operating System Compatibility	Windows, Mac OS, Linux
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