Xerox 560 - Supported Media

Condition code settings:
2 3
4 Result in R
0 0
Zero
0
Negative
0
Positive
Note: Write locks protect memory and traps are not in-
hibited during the execution of LAS.
LS LOAD SELECTIVE
(Word index alignment)
Register Ru 1 contains a 32-bit mask. If R is an even value,
LOAD SELECTIVE loads the effective word into register R
in those bit positions selected by a 1 in corresponding bit
positions of register Ru 1. The contents of register R are not
affected in those bit positions selected by a 0 in corre-
sponding bit positions of register Rul.
If R is an odd value, LS logically ANDs the contents of
register R with the effective word and loads the result into
register R. If corresponding bit positions of register Rand
the effective word both contain lis, a 1 remains in reg-
ister R; otherwise, a 0 is placed in the corresponding bit
position of register R.
Affected: (R), CC3, CC4
If R is even, [EWn(Rul)] u [(R)n(Rul)]-R
If R is odd, EWn(R) - R
Condition code settings:
2 3 4 Result in R
-
0 0 Zero.
- 0 Bit 0 of register R is a 1.
OBit 0 of register Ris a 0 andbitpositions 1-31
of register R contain at least one 1.
Example 1,
even R field value:
Before execution
After execution
r' ~,
-
X
'
01234567
1
X
'
01234567
1
C vv
(Ru 1)
XI FFOOFFOO
'
XI FFOOFFOO
'
(R)
xxxxxxxx
X
'
Ol xx45xx
'
CC
xxxx
xx 10
54 Load/Store Instructions
Example
2, odd R field value:
Before execution
After execution
EW
X
'
89ABCDEF
'
X
'
89ABCDEF
'
(R)
XI FOFOFOFO
'
X
'
80AOCOEO
'
CC
xxxx
xxOl
LM
LOAD MULTIPLE
(Word index alignment)
LOAD MULTIPLE loads a sequential set of words into a se-
quenti a I set of registers, the set of words to be loaded begins
with the word pointed to by the effective address of LM,
and the set of registers begins with register R. The set of
registers is treated modulo 16 (i. e., the next register loaded
after register 15 is register 0 in the current register block).
The number of words to be loaded into the general registers
is determined by the setting of the condition code immedi-
atey before the execution of LM. (The desired value of the
condition code can be set with LCF or LCFI.) An initia I
value of 0000 for the condition code causes 16 consecutive
words to be loaded into the register block.
Affected: (R) to (R-tCC-l)
(EWL - R; (EWL + 1) - R+ 1), ... , (EWL -tCC-l) - R-tCC-l
The
LM instruction may cause a trap if its operation ex-
tends into a page of memory that is protected by the access
protection codes. A trap may also occur if the operation
extends into a nonexistent memory region.
If the effective virtual address of the LM instruction is in
the range 0 through 15, then the words to be loaded are
taken from the general registers rather than from main mem-
nrv Tn thi~ r:n~p thp rp~lIlt~ will hp IInnrpriir:tnhlp if nn\l nf
_./. _ ...... - ----- ... - ._-_ .. - ..... -- _ ...... _-.-._-._ .. _ ... ,_.
the source registers are also used as destination registers.
LCFI LOAD CONDITIONS AND FLOATING
CONTROL IMMEDIATE
(Immedi
ate operand)
If bit position 10 of the instruction word contains a 1, LOAD
CONDITIONS AND FLOATING CONTROL IMMEDIATE
loads the contents of bit positions 24 through 27 of the in-
struction word into the condition code; however, if bit 10
is 0, the condition code is not affected.
If bit position 11 of the instruction word contains a 1,
LCFI loads the contents of bit positions 28 through 31 of
the instruction word into the floating round (FR), floating