original
contents
of
register
R,
register
Rul,
CC1,
CC3,
and
CC4
unchangedj
otherwise,
the
BP
executes
the
next
instruction in
sequence.
AWM
ADD
WORD TO MEMORy
t
0/Vord
index
alignment)
ADD
WORD TO MEMORY adds
the
contents
of
register
R
to the
effective
word and stores
the
sum in
the
effective
word
location.
The
sum
is stored regardless
of
whether
or
not
overflow
occurs.
Affected:
(EWL),
CC
Trap:
Fixed-pointoverflow
EW
+
(R)
-EWL
Condition
code
settings:
2 3 4 Result in
EWL
- 0 0 Zero
- 0
Negative
o Positive
- 0
No
fixed-point
overflow
Fixed-point
overflow
o
No
cnrrv
from
hit
nnc::itinn
n
I -
--
-
.-
- -
..
-
-"
-
Carry
from
bit
position 0
If CC2 is
set
to 1 and
fixed-point
arithmetic
trap
mask
(AM) is a 1,
the
BP
traps to
location
X
'
43
1
after
the
re-
sult
is stored in
the
effective
word
locationj
otherwise,
the
BP
executes
the
next
instruction in
sequence.
MTB
MODIFY AND
TEST
BYTE
t
(Byte
index
alignment)
If the
value
of
the
R
field
is
nonzero,
the
high-order
bit
of
the R field (bit position 8
of
the
instruction
word)
is
ex-
tended
4
bit
positions to
the
left,
to form a
byte
with
bit
positions
0-4
of
that
byte
equal to
the
high-order
bit
of
tThis
instruction
requires two memory
references
to the same
location
for its
execution.
To
preclude
other
processors
from
accessing
the
effective
location
during this
time,
the
memory
unit
containing
the
effective
location
is reserved
(not
accessible
to
other
processors) unti I
the
instruction
is
completed.
the
R
field.
This
byte
is
added
to
the
effective
byte
and
then (if no memory
protection
violation
occurs) the
sum
is
stored in
the
effective
byte
location
and
the
condition
code
is
set
according
to
the
value
of
the
resultant
byte.
This
process
allows
modification
of
a
byte
by
any
number in
the
range
-8
through +7, followed by a
test.
If
the
value
of
the
R
field
is
zero,
the
effective
byte
is
tested
for being a
zero
or
nonzero
value.
The
condition
code
is
set
according
to
the
result
of
the
test,
but
the
effective
byte
is
not
affected.
A memory
write-protection
violation
cannot
occur
in this
casej
however,
a memory
read-protection
violation
can
occur.
Affected:
CC
if
(1)8-11/0
(EBL)
and
CC
if
(1)8-11
-10
If (1)8-11
-10,
EB
+ (1)8-11
SE
-
EBL
and
set
CC
If
(1)8-11 =
0,
test
byte
and
set
CC
Condi ti on
code
setti
ngs:
2 3 4 Result in
EBL
- 0 0 0
Zero
- 0
o
Nonzero
o
No
carry
from
byte
-
Carry
from
byte
!f
~.ATB
:!:
~~(!~:..;tcd
;~
(::i'i
;iitCii;';p~
vi
!'iup
:0CCitiv{t, the
condition
code
is
not
affected
and
a
20-bit
reference
ad-
dress is used, as
described
under
"Interrupt
and Trap Entry
Addressing",
Chapter
2.
Note:
All "Modify and Test" instructions in
interrupt
loca-
tions
other
than
Counter
4 use
real,
or
real
extended,
addressing mode.
Counter
4 uses virtual addressing
mode.
MTH
MODIFY
AND
TEST
HALFWORD
t
(Halfword
index
alignment)
If
the
value
of
the R field is
nonzero,
the
high-order
bit
of
the
R
field
(bit position 8
of
the
instruction
word) is
ex-
tended
12
bit
positions to the
left,
to form a halfword with
bit
positions
0-11
of
that
halfword
equal
to
the
high-order
bit
of
the
R
field.
This halfword is
added
to
the
effective
halfword and then (if no memory
protection
violation
oc-
curs)
the
sum
is stored in
the
effective
halfword
location
and
the
condition
code
is
set
according
to
the
value
of
the
resultant
halfword. The
sum
is stored regardless
of
whether
or
not
overflow
occurs.
This process allows modification
of
a halfword by
any
number in
the
range
-8
through +7,
fol-
lowed by a
test.
Fixed-Point
Arithmetic
Instructions
65
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