Xilinx ChipScope Pro User Manual

204 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 5: ChipScope Engine Tcl Interface
::chipscope::csevio_read_values
Reads values from the specified signal/bus of the target VIO core.
Syntax
::chipscope::csevio_read_values handle [list deviceIndex userRegNumber
coreIndex] inputTclArray
Arguments
Returns
An exception is thrown if the command fails.
Example
Assumptions for this example:
• coreRef has already been set to the VIO core.
• A signal called “status” is defined as a bit in the SYNC_INPUT port.
• A bus called “data_bus” is defined as an 8-bit bus in the ASYNC_INPUT port.
1. Get the values of “status” and “data_bus” and print them to stdout
%csevio_read_values $handle $coreRef inputTclArray
Table 5-70: Arguments for Subcommand ::chipscope::csevio_read_values
Argument Type Description
handle
Required
Handle to the session that is returned by
::chipscope::csejtag_session create
[list
deviceIndex
userRegNumber
coreIndex]
A list containing three elements:
• Device index (0 to n-1) in the n-length JTAG chain
• BSCAN block USER register number (starting with 1)
• Index for core unit. First core unit connected to ICON has
index 0.
inputTclArray Name of a Tcl array. The index into the array is the name of
an input signal or bus defined by
csevio_define_signal or csevio_define_bus,
respectively. Special postfixes can be used to specify various
states of the input signal or buses:
• “.value” specifies the signal/bus value (same as no
postfix)
• “.activity_up” specifies asynchronous low-to-high
activity
• “.activity_down” specifies asynchronous high-to-
low activity
• “.sync_activity_up” specifies the synchronous
low-to-high activity (only valid for SYNC_INPUT
signals/buses)
• “.sync_activity_down” specifies the synchronous
high-to-low activity (only valid for SYNC_INPUT
signals/buses)

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English

Summary

Chapter 1: Introduction

ChipScope Pro Tools Overview

Overview of ChipScope Pro tools for FPGA debugging and analysis.

ChipScope Pro Tools Description

Brief description of various ChipScope Pro tools and cores.

System Requirements

Outlines the necessary operating system and software tools for ChipScope Pro.

Chapter 2: Using the Core Generator Tools

Overview

Introduction to using the Xilinx CORE Generator tool for ChipScope Pro cores.

Generating Cores for ICON, ILA, VIO and ATC2 Cores

Instructions for generating ICON, ILA, VIO, and ATC2 cores.

Chapter 3: Using the ChipScope Pro Core Inserter

ChipScope Pro Core Inserter Overview

Description of the post-synthesis tool for inserting debug cores.

Using the ChipScope Pro Core Inserter with ISE Project Navigator

Guide for integrating the Core Inserter with Project Navigator.

ChipScope Pro Core Inserter Features

Details on working with projects, preferences, and inserting cores.

Chapter 4: Using the ChipScope Pro Analyzer

ChipScope Pro Analyzer Overview

Introduction to the ChipScope Pro Analyzer tool for debugging.

ChipScope Pro Analyzer Client Interface

Description of the GUI components of the ChipScope Pro Analyzer client.

Trigger Setup Window

Configuration interface for setting up triggers for ILA cores.

Waveform Window

Displays captured data as a waveform, similar to logic analyzers.

Chapter 5: ChipScope Engine Tcl Interface

Overview

Introduction to Tcl scripting access for JTAG and ChipScope cores.

CSE/Tcl Command Summary

Summary of CSE/Tcl commands categorized for JTAG, FPGA, and cores.

CseJtag Tcl Commands

Detailed description of JTAG interface status and control commands.

Appendix A: ChipScope Pro Tools Troubleshooting Guide

ChipScope Pro Tools Installation Troubleshooting

Guidance on common errors and issues with ChipScope Pro tool installation.

Xilinx JTAG Programming Cable Troubleshooting

How to troubleshoot common Xilinx JTAG cable connection issues.

ChipScope Pro Analyzer Core Troubleshooting

Deals with issues in core detection, triggering, and data display.

Appendix B: References

Documents specific to multi-gigabit serial transceivers:

Lists documents related to multi-gigabit serial transceivers.

Xilinx Tools and Solutions

References to Xilinx tools and solutions documentation.