Xilinx ChipScope Pro User Manual

200 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 5: ChipScope Engine Tcl Interface
::chipscope::csevio_define_signal
Defines a name for a specified VIO signal bit. Requires that csevio_init_core be called
first.
Syntax
::chipscope::csevio_define_signal handle [list deviceIndex
userRegNumber coreIndex] name flags bitIndex
Arguments
Returns
An exception is thrown if the command fails.
Example
For the VIO core connected to ICON core inside fourth device on second USER register,
define a signal called
status_bit that is assigned to bit 0 of the ASYNC_INPUT port:
%set coreRef [list 3 2 0]
%set csevio_define_signal $handle $coreRef “status_bit”
$CSEVIO_ASYNC_INPUT 0
Back to list of all CseVIO Tcl Commands
Table 5-66: Arguments for Subcommand ::chipscope::csevio_define_signal
Argument Type Description
handle
Required
Handle to the session that is returned by
::chipscope::csejtag_session create
[list
deviceIndex
userRegNumber
coreIndex]
A list containing three elements:
• Device index (0 to n-1) in the n-length JTAG chain
• BSCAN block USER register number (starting with 1)
• Index for core unit. First core unit connected to ICON
has index 0.
name Name to be given to the signal. All input signal names
must be unique with respect to other input signals. All
output signal names must be unique with respect to
other output signals.
flags Flags used to determine the port type to which the signal
belongs. Possible flag values include:
• $CSEVIO_SYNC_OUTPUT
• $CSEVIO_SYNC_INPUT
• $CSEVIO_ASYNC_OUTPUT
• $CSEVIO_ASYNC_INPUT
bitIndex Bit index into the port. Used to determine what port
signal to assign to the name.

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English