Xilinx ChipScope Pro User Manual

160 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 5: ChipScope Engine Tcl Interface
::chipscope::csejtag_tap set_irlength
This subcommand sets the instruction register (IR) length of a single device in the current
JTAG chain. The
IR length is used to determine the amount of padding required to shift an
instruction into a device register. TAP shift and navigate operations do not work until all
devices have the IR lengths set up correctly. The
::chipscope::csejtag_tap
autodetect_chain
subcommand automatically sets up IR lengths for all devices in the
chain that support the
IDCODE command.
Note: The JTAG target must be locked by using the ::chipscope::csejtag_target lock
subcommand before calling this subcommand. Also, the device count must be set prior to calling this
subcommand using the ::chipscope::csejtag_tap set_device_count.
Syntax
::chipscope::csejtag_tap set_irlength handle deviceIndex irLength
Arguments
Returns
An exception is thrown if the subcommand fails.
Example
Set the IR length of the device at index 0 to 11 bits.
%::chipscope::csejtag_tap set_irlength $handle 0 11
Back to list of all CseJtag Tcl Commands
Table 5-32: Arguments for Subcommand ::chipscope::csejtag_tap set_irlength
Argument Type Description
handle
Required
Handle to the session that is returned by
::chipscope::csejtag_session create.
deviceIndex Device index (0 to n-1) in the n-length JTAG chain.
irLength Length of the IR (in bits)

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English

Summary

Chapter 1: Introduction

ChipScope Pro Tools Overview

Overview of ChipScope Pro tools for FPGA debugging and analysis.

ChipScope Pro Tools Description

Brief description of various ChipScope Pro tools and cores.

System Requirements

Outlines the necessary operating system and software tools for ChipScope Pro.

Chapter 2: Using the Core Generator Tools

Overview

Introduction to using the Xilinx CORE Generator tool for ChipScope Pro cores.

Generating Cores for ICON, ILA, VIO and ATC2 Cores

Instructions for generating ICON, ILA, VIO, and ATC2 cores.

Chapter 3: Using the ChipScope Pro Core Inserter

ChipScope Pro Core Inserter Overview

Description of the post-synthesis tool for inserting debug cores.

Using the ChipScope Pro Core Inserter with ISE Project Navigator

Guide for integrating the Core Inserter with Project Navigator.

ChipScope Pro Core Inserter Features

Details on working with projects, preferences, and inserting cores.

Chapter 4: Using the ChipScope Pro Analyzer

ChipScope Pro Analyzer Overview

Introduction to the ChipScope Pro Analyzer tool for debugging.

ChipScope Pro Analyzer Client Interface

Description of the GUI components of the ChipScope Pro Analyzer client.

Trigger Setup Window

Configuration interface for setting up triggers for ILA cores.

Waveform Window

Displays captured data as a waveform, similar to logic analyzers.

Chapter 5: ChipScope Engine Tcl Interface

Overview

Introduction to Tcl scripting access for JTAG and ChipScope cores.

CSE/Tcl Command Summary

Summary of CSE/Tcl commands categorized for JTAG, FPGA, and cores.

CseJtag Tcl Commands

Detailed description of JTAG interface status and control commands.

Appendix A: ChipScope Pro Tools Troubleshooting Guide

ChipScope Pro Tools Installation Troubleshooting

Guidance on common errors and issues with ChipScope Pro tool installation.

Xilinx JTAG Programming Cable Troubleshooting

How to troubleshoot common Xilinx JTAG cable connection issues.

ChipScope Pro Analyzer Core Troubleshooting

Deals with issues in core detection, triggering, and data display.

Appendix B: References

Documents specific to multi-gigabit serial transceivers:

Lists documents related to multi-gigabit serial transceivers.

Xilinx Tools and Solutions

References to Xilinx tools and solutions documentation.