Xilinx ChipScope Pro User Manual

72 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 4: Using the ChipScope Pro Analyzer
If using Project Navigator, the NGD design file is typically found in the same directory
as the BIT file you used to configure the FPGA device under test.
If using the PlanAhead tool, the location of the NGD design file is typically found
under your project directory location in the sub-directory
<project>.runs/<implementation run name>(where <project> is called
"project_1" by default, and <implementation run name> is called "impl_1" by
default).
• CTJ file that contains your trigger settings.
• A UCF file that contains ILA core initialization settings that correspond to your
desired trigger settings.
Note: If you use the PlanAhead tool to implement your design, make sure you do not save your CTJ
or UCF in the implementation run directory because the PlanAhead tool deletes all files in this
directory before re-implementing your design.
After you save your trigger startup files, the ChipScope Pro Analyzer tool automatically
converts the CTJ trigger settings into UCF design constraints that must be applied to your
design. This requires you to add this new UCF file to your project and re-implement your
design using either Project Navigator or the PlanAhead tool.
Note: The startup trigger UCF file must be added to your project in addition to your original UCF
design constraint files. Only one startup trigger UCF file per ILA core should be added to your design.
After you re-implement your design and create a new BIT file, configure the device with
this BIT file using the ChipScope Pro Analyzer tool. To see if your startup trigger condition
has occurred, first change the Trigger Run Mode to Startup. The software prompts you to
specify the startup trigger files that were used during the implementation process to create
the BIT file. In Startup Trigger Run Mode, the Apply Settings and Arm Trigger and Stop
Acquisition toolbar buttons are highlighted in yellow, and the Trigger Immediate button
is disabled. Also, the Trigger S e t u p window is disabled to prevent inadvertent changes to
the trigger settings that do not match those saved in the BIT file.
Click the Run toolbar button to check the status of the ILA core. If the ILA core has
triggered, and the data capture buffer is full, the ChipScope Pro Analyzer tool uploads and
displays the captured data. If the ILA core has not triggered or if it has not completely filled
the data capture buffer, the ILA core status is displayed at the bottom of the trigger setup
window.
Note: The startup trigger mode is armed immediately only after the FPGA device emerges from the
"startup" state. To re-arm the trigger, you would need to re-configure the device. To change the
startup trigger settings, you must change the Trigger Run Mode to Single and repeat the steps
described in this section.
Trigger and Capture Status
The status of the trigger logic for each ILA core is shown in the status bar at the bottom of
the Trigger Setup window corresponding to the core. The following information is shown:
• Trigger state such as “Waiting for trigger”, “Capture started”, or “Slow or stopped
clock” is shown in the lower-left status bar.
• Capture buffer state indicating how many samples have been captured is also shown
in the lower-left status bar.
• Trigger modes, such as SINGLE RUN, REPETITIVE RUN, and IDLE are shown in
the lower-right status box.
An icon that changes to indicate the state of the trigger and capture logic for the ILA core
is also provided.

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English