Xilinx ChipScope Pro User Manual

ChipScope Pro Software and Cores User Guide www.xilinx.com 9
UG029 (v14.3) October 16, 2012
Using ChipScope Pro Cores in the PlanAhead Tool
The HDL instantiation method is a two-step process that involves:
1. Using the IP Catalog in the PlanAhead tool to select, customize, and generate the
desired ChipScope Pro debug core.
2. Using the HDL Editor in the PlanAhead tool to manually instantiate the IP component
instance into your HDL source.
The HDL instantiation method is a good approach for users who want full control of all IP
core parameters and connections to signals in their HDL design. The downside of HDL
instantiation is that it requires the user to modify their source code. It can also be difficult
to debug a design that is made up of multiple levels of hierarchy because signals of interest
need to be brought to the debug core instance.
The Netlist insertion method is also a two step process that involves:
1. Selecting signals or nets in your design that are interesting for debugging purposes.
2. Specifying how you want these signals to be attached to debug IP cores.
The PlanAhead tool takes care of generating the debug IP core, inserting it into the design
netlist, and connecting it to the nets of interest. A potential drawback to the netlist insertion
method is that the HDL signals you want to debug could be optimized away or obfuscated
during synthesis process. Most signals that are interesting for debug (such as outputs of
registers, block RAM, etc.) are not adversely affected by the synthesis process. However,
one way to ensure signals are preserved for debugging later in the flow is to attach the
MARK_DEBUG attribute or property to signals in your design source (either your HDL or
constraints files). For details about the MARK_DEBUG attribute and other constraints,
refer to the ISE Constraints Guide
[See Reference 14, p. 225].
The MARK_DEBUG property has the following benefits:
• Allows targeted debugging of signals in your design source without the overhead of
HDL instantiation method
• Ensures signals to be debugged are preserved in the synthesized netlist
• Is compatible with Xilinx Synthesis Technology (XST) and third party FPGA synthesis
tools such as Synopsys, Synplify Pro, and Mentor Graphics Precision.
For more details on the ChipScope debugging capabilities of the PlanAhead tool, refer to
the PlanAhead User Guide
[See Reference 17, p. 225].
Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows
The cores (ICON, ILA, IBA, VIO, and ATC2) can also be used in the EDK and System
Generator for DSP tool flows for embedded processor and DSP designs, respectively. For
information on how to use the ChipScope Pro cores, see the EDK Platform Studio
[See
Reference 15, p. 225] and System Generator for DSP [See Reference 19, p. 225]
documentation.

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English