Xilinx KCU116 - Page 40

KCU116 Board User Guide 40
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Table 3-9 lists the GTY Bank 227 interface connections between FPGA U1 and FMC HPC0
connector J5
For additional information on GTY transceivers, see UltraScale Architecture GTY Transceivers
User Guide (UG578) [Ref 7]. Also see UltraScale FPGAs Transceivers Wizard LogiCORE IP
Product Guide (PG182) [Ref 8]. For additional information about UltraScale PCIe
functionality, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP
Product Guide for Vivado Design Suite (PG156) [Ref 18]. For additional information about
the PCI Express standard, see [Ref 28].
Table3‐9: KCU116 FPGA U1 GTY Bank 227 Connections
GTY
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin
Name
Schematic Net Name
Connected
Pin
Connected Pin
Name
Connected
Device
GTY
Bank
227
F7 MGTYTXP0_227 FMC_HPC_DP0_C2M_P C2 DP0_C2M_P
FMC
HPC0 J5
F6 MGTYTXN0_227 FMC_HPC_DP0_C2M_N C3 DP0_C2M_N
D2 MGTYRXP0_227 FMC_HPC_DP0_M2C_P C6 DP0_M2C_P
D1 MGTYRXN0_227 FMC_HPC_DP0_M2C_N C7 DP0_M2C_N
E5 MGTYTXP1_227 FMC_HPC_DP1_C2M_P A22 DP1_C2M_P
E4 MGTYTXN1_227 FMC_HPC_DP1_C2M_N A23 DP1_C2M_N
C4 MGTYRXP1_227 FMC_HPC_DP1_M2C_P A2 DP1_M2C_P
C3 MGTYRXN1_227 FMC_HPC_DP1_M2C_N A3 DP1_M2C_N
D7 MGTYTXP2_227 FMC_HPC_DP2_C2M_P A26 DP2_C2M_P
D6 MGTYTXN2_227 FMC_HPC_DP2_C2M_N A27 DP2_C2M_N
B2 MGTYRXP2_227 FMC_HPC_DP2_M2C_P A6 DP2_M2C_P
B1 MGTYRXN2_227 FMC_HPC_DP2_M2C_N A7 DP2_M2C_N
B7 MGTYTXP3_227 FMC_HPC_DP3_C2M_P A30 DP3_C2M_P
B6 MGTYTXN3_227 FMC_HPC_DP3_C2M_N A31 DP3_C2M_N
A4 MGTYRXP3_227 FMC_HPC_DP3_M2C_P A10 DP3_M2C_P
A3 MGTYRXN3_227 FMC_HPC_DP3_M2C_N A11 DP3_M2C_N
K7 MGTREFCLK0P_227 FMC_HPC_GBTCLK0_M2C_C_P
(1)
D4 GBTCLK0_M2C_P
K6 MGTREFCLK0N_227 FMC_HPC_GBTCLK0_M2C_C_N
(1)
D5 GBTCLK0_M2C_N
H7 MGTREFCLK1P_227 FMC_HPC_GBTCLK1_M2C_C_P
(1)
B20 GBTCLK1_M2C_P
H6 MGTREFCLK1N_227 FMC_HPC_GBTCLK1_M2C_C_N
(1)
B21 GBTCLK1_M2C_N
Notes:
1. Series capacitor AC coupled.
2. MGT connections I/O standard not applicable.
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