Zynq-7000 PCB Design Guide www.xilinx.com 29
UG933 (v1.8) November 7, 2014
Chapter 3: Power Distribution System
Capacitor Placement Background
To perform the decoupling function, capacitors should be close to the device being
decoupled.
Increased spacing between the AP SoC and decoupling capacitor increases the current flow
distance in the power and ground planes, and it often increases the current path’s
inductance between the device and the capacitor.
The inductance of this current path (the loop followed by current as it travels from the V
CC
side of the capacitor to the V
CC
pin[s] of the AP SoC, and from the GND pin[s] of the AP SoC
to the GND side of the capacitor[s]), is proportional to the loop area. Inductance is
decreased by decreasing the loop area.
Shortening the distance between the device and the decoupling capacitor reduces the
inductance, resulting in a less impeded transient current flow. Because of typical PCB
dimensions, this lateral plane travel tends to be less important than the phase relationship
between the AP SoC noise source and the mounted capacitor.
The phase relationship between the AP SoC’s noise source and the mounted capacitor
determines the capacitor’s effectiveness. For a capacitor to be effective in providing
transient current at a certain frequency (for example, the capacitor’s resonant frequency),
the phase relationship, based on the distance travelled by the current from the AP SoC to
the capacitor, must be within a fraction of the corresponding period.
The capacitor’s placement determines the length of the transmission line interconnect (in
this case, the power and ground plane pair) between the capacitor and AP SoC. The
propagation delay of this interconnect is the key factor.
AP SoC noise falls into certain frequency bands, and different sizes of decoupling capacitors
take care of different frequency bands. Thus, capacitor placement requirements are
determined by each capacitor’s effective frequency.
When the AP SoC initiates a current demand change, it causes a small local disturbance in
the PDS voltage (a point in the power and ground planes). Before it can counteract this, the
decoupling capacitor must first sense a voltage difference.
A finite time delay (Equation 3-6) occurs between the start of the disturbance at the AP SoC
power pins and the point when the capacitor senses the disturbance.
Equation 3-6
The dielectric is the substrate of the PCB where the power planes are embedded.
Time Delay
Distance from the AP SoC power pins to the capacitor
Signal propagation speed through FR4 dielectric
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