Xilinx Zynq-7000 Design Guide

Zynq-7000 PCB Design Guide www.xilinx.com 12
UG933 (v1.8) November 7, 2014
Chapter 3
Power Distribution System
Introduction
This chapter documents the power distribution system (PDS) for Zynq-7000 AP SoC devices,
including decoupling capacitor selection, placement, and PCB geometries. A simple
decoupling method is provided for each device. Basic PDS design principles are covered, as
well as simulation and analysis methods. This chapter contains the following sections:
• PCB Decoupling Capacitors
• Basic PDS Principles
• Simulation Methods
• PDS Measurements
• Troubleshooting
PCB Decoupling Capacitors
Recommended PCB Capacitors per Device
A simple PCB-decoupling network for the Zynq-7000 AP SoC devices is listed in Table 3-1
and Table 3- 2. The optimized quantities of PCB decoupling capacitors assumes that the
voltage regulators have stable output voltages and meet the regulator manufacturer's
minimum output capacitance requirement.
Decoupling methods other than those presented in these tables can be used, but the
decoupling network should be designed to meet or exceed the performance of the simple
decoupling networks presented here. The impedance of the alternate network must be less
than or equal to that of the recommended network across frequencies from 100 KHz to
100 MHz.
Because device capacitance requirements vary with CLB and I/O utilization, PCB decoupling
guidelines are provided on a per-device basis. V
CCINT
, V
CCAUX
, V
CCAUX_IO
, V
CCBRAM
, and PS
supply capacitors are listed as the quantity per device, while V
CCO
capacitors are listed as
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English