Zynq-7000 PCB Design Guide www.xilinx.com 39
UG933 (v1.8) November 7, 2014
Chapter 4
SelectIO Signaling
Introduction
The Zynq-7000 AP SoC SelectIO resources are the general-purpose I/O and its various
settings. With numerous I/O standards and hundreds of variants within these standards,
these SelectIO resources offer a flexible array of choices for designing I/O interfaces.
This chapter provides some strategies for choosing I/O standard, topography, and
termination, and offers guidance on simulation and measurement for more detailed
decision making and verification. In many cases, higher-level aspects of the system (other
device choices or standards support) define the I/O interfaces to be used. In cases where
such constraints are not defined, it is up to the system designer to choose I/O interface
standards and optimize them according to the purpose of the system.
This chapter contains the following sections:
• Interface Types
• Single-Ended Signaling
Interface Types
To better address the specifics of the various interface types, it is necessary to first break
interfaces into categories. Two relevant divisions are made:
• Single-Ended interfaces versus Differential interfaces
• Single Data Rate (SDR) interfaces versus Double Data Rate (DDR) interfaces
Single-Ended versus Differential Interfaces
Traditional digital logic uses single-ended signaling – a convention that transmits a signal
and assumes a GND common to the driver and receiver. In single-ended interfaces, a
signal’s assertion (whether it is High or Low) is based on its voltage level relative to a fixed
voltage threshold that is referenced to GND. When the voltage of the signal is higher than
the V
IH
threshold, the state is considered High. When the voltage of the signal is lower than
To Next Page
Loading...
Need help?
General
