Zynq-7000 PCB Design Guide www.xilinx.com 56
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
PS Clock and Reset
PS_CLK – Processor Clock
PS_CLK shall be connected to a clock generator providing a 30-60 MHz clock. The clock
must be a single-ended LVCMOS signal, using the same voltage level as the V
CCO_MIO0
I/O
voltage for bank MIO0. Refer to DS187
, Zynq-7000 All Programmable SoC (Z-7010, Z-7015,
and Z-7020): DC and AC Switching Characteristics and DS191
, Zynq-7000 All Programmable
SoC (Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics for further PS_CLK
requirements.
PS_POR_B – Power on Reset
The PS power-on reset (PS_POR_B) is an active-Low signal used to hold the PS in reset until
all PS power supplies are stable and at their required voltage levels. It is suggested to
generate this signal from the power supply power-good signal or a voltage supervisor chip.
PS_SRST_B – External System Reset
The PS system reset (PS_SRST_B) is an active-Low signal that is mostly used for debugging proposes.
PS_SRST_B must be High to begin the boot process. If PS_SRST_B is not used it can be pulled High to
V
CCO_MIO1
.
Boot Mode Pin MIO[8]
MIO[8] is used to configure the boot mode, PLL bypass, and MIO voltage. All designs must
include a 20 KΩ pull-up or pull-down resistor on this pin to set the required setting.
MIO[8] is a dual use pin that is shared with the high-speed QSPI/NAND/SRAM interface
signals. Special care needs to be taken to avoid signal integrity issues. To avoid signal
integrity issues, limit the stub length to the pull-up or pull-down resistor to < 10 mm.
When system design requires the modes to be changeable, it is recommended to not use a
resistor tree to set the mode but instead connect one pull-up/down resistor to the mode
pin and place a jumper on the other side of the resistor to select between pull-up or
pull-down. See Figure 5-4 for an example.
Note:
PROGRAM_B, INIT_B, and DONE should not be left floating. Refer to UG470, 7 Series FPGAs
Configuration User Guide for more information on how to treat these pins.
Note: The PL system JTAG interface, PL_JTAG, should have its signals TDI, TMS, and TCK pulled-up.
To Next Page
Loading...
Need help?
General
