Xilinx Zynq-7000 Design Guide

Zynq-7000 PCB Design Guide www.xilinx.com 60
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
X-Ref Target - Figure 5-6
Figure 5-6: DDR2 Board Implementation
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF VDDQ
VREF
VTT
VREF
VTT
VDDQ
VDDQ
VDDQ
DDR
Termination
Regulator
VTT
Rterm
Rdown
VREF VDDQ
VREF VDDQ
Addr, Command, Contrl
(Addr, we_b, ras_b,
cas_b, cs_b)
Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
cke
cke cke
cke
Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
Addr, Command, Contrl (Addr,
we_b, ras_b, cas_b, odt, cs_b)
CLK_P
CLK_N
Cke
VRN
VRP
Data Group 0
(dq, dqs, dm)
Data Group 1
(dq, dqs, dm)
Data Group 2
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
UG933_c5_05_020614
Data Group 3
(dq, dqs, dm)
Rvrnp
Rvrnp
ZYNQ
DDR2 DDR2
DDR2 DDR2
Rclk
CLK
_P_N
CLK
_P_N
Rdown
ODT
CLK
_P_N
CLK
_P_N
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V