Zynq-7000 PCB Design Guide www.xilinx.com 30
UG933 (v1.8) November 7, 2014
Chapter 3: Power Distribution System
Another delay of the same duration occurs when the compensation current from the
capacitor flows to the AP SoC. For any transient current demand in the AP SoC, a round-trip
delay occurs before any relief is seen at the AP SoC.
• Negligible energy is transferred to the AP SoC with placement distances greater than
one quarter of a demand frequency’s wavelength.
• Energy transferred to the AP SoC increases from 0% at one-quarter of a wavelength to
100% at zero distance.
• Energy is transferred efficiently from the capacitor to the AP SoC when capacitor
placement is at a fraction of a quarter wavelength of the AP SoC power pins. This
fraction should be small because the capacitor is also effective at some frequencies
(shorter wavelengths) above its resonant frequency.
One-tenth of a quarter wavelength is a good target for most practical applications and
leads to placing a capacitor within one-fortieth of a wavelength of the power pins it is
decoupling. The wavelength corresponds to the capacitor's mounted resonant frequency,
F
RIS
.
When using large numbers of external termination resistors or passive power filtering for
transceivers, priority should be given to these over the decoupling capacitors. Moving away
from the device in concentric rings, the termination resistors and transceiver supply
filtering should be closest to the device, followed by the smallest-value decoupling
capacitors, then the larger-value decoupling capacitors.
V
REF
Stabilization Capacitors
In V
REF
supply stabilization, one capacitor per pin is placed as close as possible to the V
REF
pin. The capacitors used are in the 0.01 µF – 0.47 µF range. The V
REF
capacitor’s primary
function is to reduce the V
REF
node impedance, which in turn reduces crosstalk coupling.
Since no low-frequency energy is needed, larger capacitors are not necessary.
This only applies when Internal V
REF
is not used. Internal VREF is a feature in the Zynq-7000
AP SoC device wherein the reference voltage rail is generated internally, which in turn
allows the V
REF
pins to be used as regular I/O pins. See UG471, 7 Series FPGAs SelectIO User
Guide for more details on Internal V
REF
.
Power Supply Consolidation
Powering 1.8V V
CCO
and V
CCAUX
from a common PCB plane is allowed in Zynq-7000 AP SoC
designs. However, careful consideration must be given to power supply noise—in particular,
any noise on the V
CCO
rail should not violate the recommended operating condition range
for the V
CCAUX
supply. See DS187, Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and
Z-7020): DC and AC Switching Characteristics and DS191
, Zynq-7000 All Programmable SoC
(Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics.
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