Xilinx Zynq-7000 Design Guide

Zynq-7000 PCB Design Guide www.xilinx.com 59
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
X-Ref Target - Figure 5-5
Figure 5-5: DDR3/3L Board Implementation
VREF VDDQ
VREF VDDQ
VREF VDDQ
Addr, Command,
Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
Addr, Command, Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
clk
CLK_P
CLK_N
CKE
DRST_B
Cke
rset_b
clk clk clk
Addr, Command,
Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
Addr, Command,
Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
Addr, Command,
Contrl
(Addr, we_b,
ras_b, cas_b,
odt, cs_b)
VREF VDDQ
VREF VDDQ VREF VDDQ VREF VDDQ
VREF VDDQ VREF VDDQ VREF VDDQ
VTT
Rterm
Rclk
Rzq
UG585_c30_04_022814
ZQ
ZQ
ZQ
ZQ
Rzq
Data Group
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
Data Group
(dq, dqs, dm)
VRN
VRP
VREF
VTT
VREF
VTT
VDDQ
VDDQ
Data Group
(dq, dqs, dm)
Data Group 0
(dq, dqs, dm)
Data Group 1
(dq, dqs, dm)
Data Group 2
(dq, dqs, dm)
Data Group 3
(dq, dqs, dm)
Rzq
Rvrnp
Rzq
Rdown
Cke
rset_b
Cke
rset_b
Cke
rset_b
Rvrnp
Rterm
VTT
ZYNQ DDR3
DDR3
DDR
Termination
Regulator
DDR3 DDR3
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V