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Xilinx Zynq-7000 Design Guide

Xilinx Zynq-7000
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Zynq-7000 PCB Design Guide www.xilinx.com 75
UG933 (v1.8) November 7, 2014
Appendix A: Additional Resources and Legal Notices
Xilinx ISE Design Suite
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/i
se_design_suite.html
Xilinx Embedded Development Kit (EDK)
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/
embedded_development_kit__edk.html
ChipScope Pro Documentation
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/
chipscope_pro.html
Xilinx Problem Solvers
http://www.xilinx.com/support/troubleshoot.htm
Third-Party IP and Standards Documents
To learn about functional details related to vendor IP cores contained in Zynq-7000 devices
or related international interface standards, refer the following documents:
Note:
ARM documents can be found at: http://infocenter.arm.com/help/index.jsp
°
ARM AMBA Level 2 Cache Controller (L2C-310) TRM (also called PL310)
°
ARM AMBA Specification Revision 2.0, 1999 (IHI 0011A)
°
ARM Architecture Reference Manual (Need to register with ARM)
°
ARM Cortex-A Series Programmer's Guide
°
ARM Cortex-A9 Technical Reference Manual, Revision r3p0
°
ARM Cortex-A9 MPCore Technical Reference Manual, Revision r3p0 (DDI0407F) –
includes descriptions for accelerator coherency port (ACP), CPU private timers and
watchdog timers (AWDT), event bus, general interrupt controller (GIC), and snoop
control unit (SCU)
°
ARM Cortex-A9 NEON Media Processing Engine Technical Reference Manual, Revision
r3p0
°
ARM Cortex-A9 Floating-Point Unit Technical Reference Manual, Revision r3p0
°
ARM CoreSight v1.0 Architecture Specification – includes descriptions for ATB Bus,
and Authentication
°
ARM CoreSight Program Flow Trace Architecture Specification
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Xilinx Zynq-7000 Specifications

General IconGeneral
SeriesZynq-7000
Number of CoresDual-core
Processor SpeedUp to 1 GHz
Device TypeSoC
Logic CellsUp to 350K
DSP SlicesUp to 900
External Memory InterfacesDDR3, DDR2, LPDDR2
I/O StandardsLVCMOS, HSTL, SSTL
Operating Temperature-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package OptionsVarious BGA packages
I/O Voltage3.3V

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