YOKOGAWA DL9000 Series User Manual

6-74
IM 701310-01E
Explanation
This function triggers on UART signals.
Note that the /F5, /F7, or /F8 option is required to analyze UART signals.
Mode
The mode is fixed to Every Data. This feature triggers on the stop bit of all data frames.
Data
7 bits (b0 to b6)
8 bits (b0 to b7)
Parity
Bit
Stop
Bit
Start
Bit
No parity bit if NonParity
is selected
(Positive logic)
Triggers here
Source
You can select the source from CH1 to CH4.
Bit Rate
You can select the UART bus signal transfer rate from the following:
115200 bps, 57600 bps, 38400 bps, 19200 bps, 9600 bps, 4800 bps, 2400 bps, and
1200 bps
If you select the User check box, you can set the transfer rate from 1000 bps to 200000
bps in 100-bps steps.
Format
You can select the format from the following:
8bit + Parity 8-bit data + parity bit
7bit + Parity 7-bit data + parity bit
8bit(NonParity) 8-bit data with no parity bit
Trigger Level
You can set the UART signal trigger level for CH1 to CH4 separately.
• The selectable range is 8 divisions within the screen. The resolution is 0.01 divisions.
For example, if the T/div setting is 2 mV/division, the resolution is 0.02 mV
.
• Y
ou can reset the trigger level to the current offset voltage by pressing RESET.
Hysteresis
See section 6.5 for details.
Polarity
You can select the bit state that will be considered logical 1.
Pos Positive logic
Neg Negative logic
Note
You cannot set the hold-off time when the UART signal trigger feature is enabled. For details on
the hold-off time, see section 6.4.
6.19 Triggering on a UART Signal

YOKOGAWA DL9000 Series Specifications

General

Brand	YOKOGAWA
Model	DL9000 Series
Category	Test Equipment
Language	English